[2027 Internship] Standard Cell Library Design Engineer Intern

MediaTek; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

MediaTek Singapore is seeking an entry-level IC design engineer to contribute to standard cell characterization for cutting-edge nodes (7nm/5nm/4nm/3nm) and to help set up the design platform for MediaTek projects. You will participate in modeling, flow development, and big data analysis to support our advanced processes.

Candidates should have an Engineering/CS/EE degree, basic IC/circuit design knowledge, and familiarity with UNIX/Linux and scripting languages (Python, Tcl, Perl, C/C++).

Qualifications

• Degree in Engineering/CS/EE is required.
• Basic IC/circuit design knowledge is expected.
• Familiar with UNIX/Linux and at least one programming language.
• Knowledge of SPICE simulation is a plus.

Responsibilities

• Characterize standard cell libraries for leading-edge nodes.
• Develop timing, power, constraint, noise, and variability modeling and flows for >15K logic circuits.
• Testchip design and data analysis flow development for advanced technology nodes (<7nm).

Skills

IC design

Python / scripting

UNIX / Linux

C / C++

Data analysis / ML basics

Education

Engineering/CS/EE degree

Tools

CAD tools

SPICE simulation

Job description

Job Description

[What you will do]

• Responsible for Standard Cell Library Characterization for leading edge process node (7nm/5nm/4nm/3nm), as the pioneer to setup design platform for MediaTek projects.
• Perform timing/ power/ constraint/ noise/ variation modeling, analysis and flow development for >15K logic circuit for one process node.
• Testchip design and Si data analysis flow development for advanced technology node (<7nm), including big data processing and visualization.

• Responsible for Standard Cell Library Characterization for leading edge process node (7nm/5nm/4nm/3nm), as the pioneer to setup design platform for MediaTek projects.
• Perform timing/ power/ constraint/ noise/ variation modeling, analysis and flow development for >15K logic circuit for one process node.
• Testchip design and Si data analysis flow development for advanced technology node (<7nm), including big data processing and visualization.

Main Requirements and Qualifications

• [What you will bring]
• Engineering/Computer Engineering/Computer Science, no prior experience is required.
• Basic knowledge of IC design and circuit design.
• Basic knowledge of UNIX/LINUX environment and any programming language, e.g. Python, Perl, Tcl, C/C++.
• Familiar with foundation IP (Std-cell, Memory, I/O) design and/or CAD is a plus.
• Knowledge of spice simulation, data analysis, machine learning is a plus.