[2027 Internship] Custom IC Layout Engineer Intern

MediaTek Research Lab Inc.; Singapore; On-site; SGD 11,000 - 19,000; Full time

Job summary

MediaTek Research Lab Inc. in Singapore invites you to join as a Custom IC Layout Engineer Intern to see how microchips are designed and implemented from scratch and gain hands-on experience with real projects.

You will learn the fundamentals of Physical Design, contribute to floor-planning, device placement, and routing, and collaborate with a passionate team to optimize chips for Power, Performance and Area using Cadence, Synopsys, and Siemens.

Qualifications

• You’re currently studying Electrical, Electronic, or Material Science Engineering.
• You love physics, MOS devices, and figuring out how things work.
• You’re a hands-on problem solver who enjoys cracking tough challenges.
• You’re self-driven, a great communicator, and ready to learn.

Responsibilities

• Get a behind-the-scenes look at how microchips are designed and implemented from scratch.
• Learn the essentials of Physical Design (aka Layout) for Integrated Circuits – no prior experience needed.
• Be part of a passionate team working on cutting-edge Foundation IP, Analog IP, or RFIC using the latest CMOS technology.
• Master industry-standard EDA tools (Cadence, Synopsys, Siemens) and build real layouts for real projects.
• Work on live assignments: floor-planning, device placement, signal routing, debugging, and more.
• Collaborate with experts and other interns to optimize chips for Power, Performance, and Area (PPA).
• Boost your resume with hands-on experience that top tech companies are looking for#LI-WC1

Skills

Hands-on problem solving

Communication

Education

Electrical/Electronic/Material Science Engineering

Tools

Cadence

Synopsys

Siemens

Job description

Category

Chip Design

Location

Singapore

Experience

No Work Expe.

Job Description

Curious about how the tiny chips inside your phone, laptop, or smartwatch are actually made? Want to get hands-on with the tech that powers the future? Join us as a Custom IC Layout Engineer Intern and dive into the world of microchip design![What’s in it for you?]

• Get a behind-the-scenes look at how microchips are designed and implemented from scratch
• Learn the essentials of Physical Design (aka Layout) for Integrated Circuits – no prior experience needed
• Be part of a passionate team working on cutting-edge Foundation IP, Analog IP, or RFIC using the latest CMOS technology
• Master industry-standard EDA tools (Cadence, Synopsys, Siemens) and build real layouts for real projects
• Work on live assignments: floor-planning, device placement, signal routing, debugging, and more
• Collaborate with experts and other interns to optimize chips for Power, Performance, and Area (PPA)
• Boost your resume with hands-on experience that top tech companies are looking for#LI-WC1

Main Requirements and Qualifications

• [What you will bring]
• You’re currently studying Electrical, Electronic, or Material Science Engineering
• You love physics, MOS devices, and figuring out how things work
• You’re a hands-on problem solver who enjoys cracking tough challenges
• You’re self-driven, a great communicator, and ready to learn