[2027 Internship] Mixed Signal Verification Intern

MediaTek; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

MediaTek is seeking a skilled engineer in Singapore to verify digital IC blocks within RF/Analog IPs and build macro models for system-level co-simulation.

The role involves developing Verilog/WREAL models for RF Calibration Engines and RF leaf cells, and constructing RF-digital test-bench templates for RF designers. Knowledge in digital design and Verilog HDL is advantageous.

Qualifications

• Experience in RF/Analog behavioural modelling preferred.
• Knowledge of digital design and Verilog HDL is a plus.

Responsibilities

• Verify digital IC blocks within RF/Analog IPs.
• Create analog/RF macro models for system level co-simulation verification.
• Verilog/WREAL models for RF Calibration Engines and RF Analog leaf cells.
• Build RF-digital test-bench template for RF designers.

Skills

RF/Analog modelling

Digital design

Tools

Verilog HDL

Job description

Job Description

[What you will do] - Verification of digital IC circuit blocks within analog/RF IPs - Create analog/RF macro models for system level co-simulation verification - Verilog/WREAL Models for all RF Calibration Engines - Verilog/WREAL Models for all RF Analog leaf cells - Build RF-digital test-bench template for RF designers

Main Requirements and Qualifications

• [Are you the right talent?]
• - Keen interest in RF/Analog behavioral modelling
• - Knowledge of digital design and Verilog HDL are an added advantage.