ASIC Backend Engineer - Lund - Remote option

Arion Recruitment Ltd; Göteborgs kommun; Remote; SEK 600,000 - 800,000; Full time

Job summary

Arion Recruitment Ltd is seeking an ASIC Backend Engineer to join their team in Göteborgs kommun, Sweden. The role involves contributing to advanced ASIC design for mobile network infrastructure, especially for the next-generation 5G network. Candidates need 5+ years of experience in ASIC backend design, expertise in EDA tools, and familiarity with Synopsys tools. Strong communication skills in English are important. The company offers an environment that promotes professional and personal growth.

Qualifications

• 5+ years of experience in ASIC backend design.
• Expertise in EDA tools, STA, and timing sign-off.
• Familiarity with Synopsys tools (Design Compiler, FusionCompiler, PrimeTime).

Responsibilities

• Work on synthesis, timing/area/power closure, STA, timing sign-off, and low-power designs.
• Develop timing constraints, and perform place & route, equivalence checking, and physical implementation.
• Collaborate within cross-functional teams for continuous improvement and knowledge sharing.

Skills

ASIC backend design

Low power designs

STA

VHDL/System Verilog

Scripting (Python, Perl, TCL)

Communication skills

Education

BSc/MSc in Electrical Engineering, Computer Science, or related field

Tools

EDA tools

Synopsys tools (Design Compiler, FusionCompiler, PrimeTime)

UNIX/Linux

Version control systems (Clear Case, Git)

Job description

Job Title

ASIC Backend Engineer (5G Network Infrastructure)

Job Description

Join our client's ASIC Backend Team to contribute to state‑of‑the‑art digital ASIC design for mobile network infrastructure products, enabling the next‑generation 5G network. You will focus on ASIC Backend and Static Timing Analysis (STA), collaborating in an Agile environment.

Responsibilities

• Work on synthesis, timing/area/power closure, STA, timing sign-off, and low‑power designs.
• Develop timing constraints, and perform place & route, equivalence checking, and physical implementation.
• Collaborate within cross‑functional teams for continuous improvement and knowledge sharing.

Requirements

• BSc/MSc in Electrical Engineering, Computer Science, or related field.
• 5+ years of experience in ASIC backend design.
• Expertise in EDA tools, STA, and timing sign-off.
• Proficient in low power designs, UPF, VHDL/System Verilog, scripting (Python, Perl, TCL).
• Familiarity with Synopsys tools (Design Compiler, FusionCompiler, PrimeTime).
• Experience with UNIX/Linux and version control systems (Clear Case, Git).
• Strong communication skills in English and a quality‑conscious mindset.

Preferred Qualifications

• Knowledge of multi‑core CPU architecture, mobile communication standards, and telecom.
• Experience with Synopsys Spyglass, Design Compiler, Formality.

Opportunities

• Work on cutting‑edge backend activities.
• Grow professionally and personally in a supportive, collaborative environment.

Please send CV to [e-mail].