ASIC Design Engineer / SOC Designer

Antmicro; Göteborgs kommun; On-site; SEK 486,066 - 702,095; Full time

Job summary

A leading technology firm in Göteborg is seeking an ASIC Design Engineer to join their innovative team. You will work on designing and optimizing ASICs while collaborating with experts in various domains. The ideal candidate should possess strong HDL expertise, knowledge of computer architecture, and be ready to tackle complex challenges. Situated in a dynamic environment, this role requires a BSc or MSc in relevant fields and the willingness to work on-site in Sweden.

Qualifications

• Expertise in HDLs such as SystemVerilog, Verilog, VHDL, or Chisel.
• Strong background in digital logic design, RTL, and ASIC development.
• Good understanding of RISC-V computer architecture is a plus.
• Working knowledge of various communication interfaces like UART, I2C, SPI, etc.

Responsibilities

• Collaborate with experts to design and optimize ASICs.
• Implement test-driven and software-oriented methodologies.
• Tackle complex challenges in interoperability and performance tuning.

Skills

HDLs (SystemVerilog, Verilog, VHDL, Chisel)

Digital logic design

Computer architecture

Verification (UVM, Cocotb)

C/C++/Rust

Python/Bash/TCL

Bus architectures (TileLink, AXI, AHB, APB, Wishbone)

Communication interfaces (UART, I2C, I3C, SPI, PCIe, USB)

Linux

Education

BSc or MSc in computer science, electrical engineering or related fields

Job description

As an ASIC Design Engineer at Antmicro, you will join a team of innovators working on new designs and tooling for state-of-the-art silicon.

You will collaborate with experts in various domains to design, implement, and optimize ASICs for datacenter, security, IoT and other applications, using test‑driven, software‑oriented methodologies. This role requires a deep understanding of digital logic and architecture, as well as a willingness to tackle complex challenges in interoperability, performance tuning, and low‑level design. A good background in topics such as hardware emulation, computer architectures, and systems integration is welcome, and openness to new approaches and incorporating productivity enhancements using open source tools into your workflow is necessary.

We are a leading developer of open source ASIC design tooling and IP, working within organizations like CHIPS Alliance and RISC‑V to push forward a more transparent, open and software‑driven ASIC ecosystem.

Requirements

• BSc or MSc in computer science, electrical engineering or related fields
• expertise in HDLs (e.g. SystemVerilog, Verilog, VHDL, Chisel)
• good understanding of computer architecture (RISC‑V experience is a plus)
• strong expertise in digital logic design, RTL, and ASIC development
• knowledge of common bus architectures like TileLink, AXI, AHB, APB, Wishbone
• knowledge of typical communication interfaces such as UART, I2C, I3C, SPI, PCIe and USB
• expertise in verification (e.g. UVM and/or Cocotb) and Continuous Integration
• understanding of the implications of working with different process design kits (PDKs)
• understanding of operating systems and low level software
• good knowledge of programming languages like C/C++/Rust
• good knowledge of scripting languages like Python/Bash/TCL
• working knowledge of Linux
• permanent residency and eligibility to work in the EU
• readiness to work on‑site

If you meet the listed criteria and want to join our team, hit the Apply button or fill in the application form at https://careers.antmicro.com/jobs/asic-engineer/

We reserve the right to reply only to selected applications.

Please include the following in your CV:

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