FPGA Engineer – Optical Link

LusoSpace Lda; Porto; Presencial; EUR 35 000 - 55 000; Tempo integral

Resumo da oferta

LusoSpace Lda in Porto, Portugal, is looking for a skilled FPGA Design Engineer to develop cutting-edge technologies for Optical Communication. The ideal candidate will have a solid background in digital communications, particularly in DSP, and will be engaged in designing high-speed systems that ensure reliable data transmission.

A Bachelor's degree in Telecommunications or Electronics Engineering is required, while a Master's degree is considered an asset. Proficiency in Verilog and FPGA tools such as Vivado/Quartus is essential for success in this role.

Qualificações

• Bachelor's degree in Telecommunications or Electronics Engineering.
• Master's degree is advantageous.
• Understanding of digital filters and closed-loop systems.

Responsabilidades

• Design and implement high-speed DSP blocks.
• Develop the transmit/receive path with FEC.
• Optimize FPGA for optical links.
• Interface with ADCs/DACs.
• Conduct simulations and HIL testing.

Conhecimentos

Knowledge in Verilog

Comms Protocols understanding

DSP for Control

Experience with FPGA hardware platforms

Proficiency in Vivado/Quartus

MATLAB/Simulink

Python for scripting/testing

Formação académica

Bachelor's degree in Telecommunications Engineering

Bachelor's degree in Electronics Engineering

Master's degree (plus)

Descrição da oferta de emprego

Role Overview

We are seeking a FPGA Design Engineer to develop our next‑generation Optical Communication Head. This role sits at the intersection of high‑speed digital communications and precision motion control. You will be responsible for developing the "brain" of our terminal—implementing the algorithms that keep our laser locked on target and the data flowing at maximum throughput.

Key Responsibilities

• Tracking & Acquisition: Design and implement high‑speed DSP blocks to process inputs from CMOS sensors; implement PID or Kalman filter‑based control loops.
• Data Encoding & Framing: Develop the transmit/receive path and Forward Error Correction (Reed‑Solomon, LDPC).
• High‑Speed Interfacing: Configure and optimize FPGA for optical links.
• System Integration: Interface with high‑speed ADCs/DACs and manage low‑latency communication between the FPGA fabric.
• Verification: Conduct bit‑accurate simulations and hardware‑in‑the‑loop (HIL) testing to ensure link reliability under atmospheric turbulence conditions.

Qualifications

Minimum Education

• Bachelor’s degree in:
  • Telecommunications Engineering
  • Electronics Engineering
• Master’s degree is a plus.

Required Skills

• Knowledge in Verilog.
• Comms Protocols: Deep understanding of the physical layer (PHY), clock recovery, and synchronization techniques.
• DSP for Control: experience implementing digital filters and closed‑loop control systems in fixed‑point logic.
• Hardware Platforms: Experience with the most common FPGA in the market.
• Tools: Proficiency in Vivado/Quartus, MATLAB/Simulink (for algorithm modeling), and Python for scripting/testing.