Remote VLSI Verification Engineer (UVM/SV)

Integral Solutions - Informatica Distributor; Warszawa; On-site; PLN 100,000 - 120,000; Full time

Job summary

Integral Solutions - Informatica Distributor is seeking a skilled Verification Engineer to enhance our VLSI team. This remote position entails verifying the functional correctness of complex digital IP blocks and SoCs.

The ideal candidate should have a minimum of 5 years of industry experience in VLSI verification, proficiency in SystemVerilog and UVM methodology, and a solid background in digital design fundamentals.

Qualifications

• 5+ years of hands-on VLSI verification experience in an industry setting.
• Solid understanding of digital design fundamentals.

Responsibilities

• Develop and maintain constrained-random UVM testbenches for RTL blocks.
• Write functional coverage models and coverage closure plans.
• Author and execute directed and random test scenarios.
• Debug simulation failures and collaborate with designers.
• Develop verification plans based on micro-architecture specifications.
• Contribute to regression infrastructure and CI/CD pipelines.
• Participate in design and spec reviews.

Skills

SystemVerilog

UVM methodology

Specman

VCS

Xcelium

ModelSim/Questa

Assertion-based verification

RTL coding

Microarchitecture concepts

Education

B.Sc. / M.Sc. / Ph.D. in Electrical Engineering, Computer Engineering, or related field

Job description

Integral Solutions - Informatica Distributor is seeking a skilled Verification Engineer to enhance our VLSI team. This remote position entails verifying the functional correctness of complex digital IP blocks and SoCs.

The ideal candidate should have a minimum of 5 years of industry experience in VLSI verification, proficiency in SystemVerilog and UVM methodology, and a solid background in digital design fundamentals.