Staff SoC/Chiplet Verification Engineer

Arteris; Kraków; On-site; PLN 150,000 - 230,000; Full time

Job summary

Arteris is seeking a Staff Hardware Verification Engineer in Krakow to design and execute robust verification strategies for SoCs and chiplets. You will work on parameterized IP verification, develop test benches in Python and C++, and collaborate with cross-functional teams to ensure correctness, performance and reliability of complex hardware IP.

The role requires 4+ years in verification, strong RTL language skills (VHDL/Verilog/SystemVerilog) and experience with VIPs/UVM.

Qualifications

• 4+ years of industry experience in verification engineering.
• Experience with RTL design/verification languages (VHDL/Verilog/SystemVerilog).
• Strong VIPs/UVM/testbeds and EDA tool usage.
• Fluent English; Polish/French bonus.

Responsibilities

• Define, document, develop and execute RTL verification test/coverage for highly parameterized IPs in Python and C++, on multiple RTL simulators.
• Maintain and improve verification workflows.
• Improve metrics and increase automation.
• Implement verification components such as BFMs or monitors used in verification test benches.

Skills

RTL verification

Python

C++

SystemVerilog

VHDL

Verilog

UVM

Shell scripting

AMBA/OCP protocols

team collaboration

Education

Master’s or Doctorate in engineering or computer science

Tools

Cadence

Synopsys

EDA tools

Job description

Arteris is seeking a Staff Hardware Verification Engineer in Krakow to design and execute robust verification strategies for SoCs and chiplets. You will work on parameterized IP verification, develop test benches in Python and C++, and collaborate with cross-functional teams to ensure correctness, performance and reliability of complex hardware IP.

The role requires 4+ years in verification, strong RTL language skills (VHDL/Verilog/SystemVerilog) and experience with VIPs/UVM.