Senior FPGA/ASIC Logic Designer — Remote & High-Impact

Ciklum; Polska; Remote; PLN 260,000 - 360,000; Full time

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Job summary

Ciklum is seeking an Expert Logic Design Engineer in Poland to lead architecture, RTL design, and optimization of FPGA/ASIC subsystems. You will tackle ultra-low-latency digital logic, clock-domain crossing, and timing closure, collaborating with system architects, software teams, and verification engineers.

The role emphasizes hands-on design leadership, end-to-end IP development, and the delivery of robust digital solutions for high-performance platforms.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related technical discipline, or equivalent practical experience
• 6+ years of professional experience in complex FPGA or ASIC digital logic design
• Expert-level proficiency in SystemVerilog RTL design (mandatory)
• Extensive experience defining digital architectures and microarchitectures for complex hardware systems
• Proven track record of independently delivering complex digital IP or subsystems from specification to implementation
• Deep understanding of RTL optimization, logic synthesis, static timing analysis (STA), and timing closure
• Strong experience optimizing digital designs for deterministic latency, high clock frequencies, resource utilization, and power efficiency
• Advanced knowledge of synchronous digital design, CDC, clocking architectures, and hardware interfaces
• Experience with simulation-based verification and debugging of complex digital systems
• Experience leading technical design reviews or mentoring senior engineers
• Background in quantum computing, semiconductor development, telecommunications, high-performance instrumentation, or similar advanced technology domains

Responsibilities

• Lead the architecture, microarchitecture, and RTL implementation of complex, high-performance FPGA/ASIC digital subsystems
• Design and optimize highly configurable, ultra-low-latency digital logic using SystemVerilog
• Drive end-to-end digital IP development, from system requirements and architectural trade-offs to RTL implementation and integration
• Make architectural decisions to optimize timing performance, latency, resource utilization, scalability, and power efficiency
• Address complex timing closure, clock-domain crossing, synchronization, and critical-path optimization challenges
• Develop advanced digital processing and control architectures, including signal processing pipelines, waveform generation, and deterministic real-time control
• Define hardware-software interfaces and collaborate with software and system architecture teams to ensure efficient system integration
• Work closely with verification engineers to define verification strategies and ensure robust functional coverage
• Review RTL designs, identify architectural and implementation risks, and provide technical guidance to other engineers
• Contribute to the evolution of FPGA-based platforms and the development of reusable digital IP for future ASIC implementations
• Drive engineering best practices, design quality, and technical improvements across the development lifecycle

Skills

SystemVerilog RTL

FPGA/ASIC design

timing closure

digital architectures

technical leadership

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

AMD Vivado

Synopsys VCS

Questa Sim

Job description

Ciklum is seeking an Expert Logic Design Engineer in Poland to lead architecture, RTL design, and optimization of FPGA/ASIC subsystems. You will tackle ultra-low-latency digital logic, clock-domain crossing, and timing closure, collaborating with system architects, software teams, and verification engineers.

The role emphasizes hands-on design leadership, end-to-end IP development, and the delivery of robust digital solutions for high-performance platforms.