Senior FPGA/ASIC Logic Design Architect — Remote

Description Ciklum; Polska; Remote; PLN 180,000 - 320,000; Full time

Benefits offered by this job

Remote work

Medical package

Udemy access

Language courses

Certifications

MyBenefit platform

Job summary

Ciklum is seeking an Expert Logic Design Engineer to join our Poland team full-time. You will lead architecture, RTL, and optimization of FPGA/ASIC digital subsystems with ultra-low latency and high performance using SystemVerilog.

The role demands strong timing closure, verification collaboration, and cross-disciplinary leadership across hardware and software teams. With AMD/Xilinx expertise, you’ll drive end-to-end IP development while addressing timing, power, and resource trade-offs in a

Qualifications

• Bachelor's or Master's in Electrical or Computer Engineering or equivalent.
• 6+ years in FPGA/ASIC digital logic design.
• Expert-level SystemVerilog RTL design.
• Experience with timing closure and STA.
• Ability to lead architecture and RTL implementations.
• Strong communication and mentoring skills.
• Experience with AMD/Xilinx platforms.
• Knowledge of PCIe/AXI interfaces.

Responsibilities

• Lead the architecture, microarchitecture, and RTL implementation of complex, high-performance FPGA/ASIC digital subsystems.
• Design and optimize highly configurable, ultra-low-latency digital logic using SystemVerilog.
• Drive end-to-end digital IP development, from system requirements and architectural trade-offs to RTL implementation and integration.
• Make architectural decisions to optimize timing performance, latency, resource utilization, scalability, and power efficiency.
• Address timing closure, clock-domain crossing, synchronization, and critical-path optimization challenges.
• Develop advanced digital processing and control architectures, including signal processing pipelines and deterministic real-time control.
• Define hardware-software interfaces and collaborate with software and system architecture teams.
• Work with verification engineers to define verification strategies and ensure robust functional coverage.
• Review RTL designs and provide guidance on risks and improvements.
• Contribute to evolution of FPGA-based platforms and reusable digital IP for future ASICs.

Skills

SystemVerilog RTL design

FPGA/ASIC architecture

Timing closure

Verification concepts

Leadership

English communication

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Xilinx Vivado

Synopsys VCS

QuestaSim

AMD Versal

Job description

Ciklum is seeking an Expert Logic Design Engineer to join our Poland team full-time. You will lead architecture, RTL, and optimization of FPGA/ASIC digital subsystems with ultra-low latency and high performance using SystemVerilog.

The role demands strong timing closure, verification collaboration, and cross-disciplinary leadership across hardware and software teams. With AMD/Xilinx expertise, you’ll drive end-to-end IP development while addressing timing, power, and resource trade-offs in a