Senior FPGA/ASIC Logic Design Engineer — Remote Options

Ciklum; Polska; Remote; PLN 120,000 - 180,000; Full time

Benefits offered by this job

Remote work flexibility

Premium medical package

Udemy access

Language courses

Company-paid certifications

MyBenefit platform

Job summary

Ciklum is seeking a Senior Logic Design Engineer in Poland to advance next-generation FPGA/ASIC platforms. You will design high-performance, low-latency RTL modules with SystemVerilog and collaborate with architects, verification, software, and hardware teams in an international setting.

Responsibilities include lifecycle design, timing optimization, and IP integration, with a focus on CDC-aware, high-speed interfaces.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 4+ years of FPGA/ASIC digital logic design experience.
• Strong SystemVerilog RTL development experience (mandatory).

Responsibilities

• Design and implement low-latency RTL modules using SystemVerilog.
• Develop digital logic for FPGA/ASIC applications, including signal processing and real-time control.
• Participate in RTL development lifecycle from architecture to verification.
• Optimize designs for timing, latency, and power.
• Perform synthesis and timing analysis to meet constraints.
• Collaborate with verification engineers for correctness and test coverage.
• Interface hardware-software with system-level requirements.
• Integrate proprietary IP into FPGA/ASIC architectures.
• Participate in design reviews and process improvements.

Skills

SystemVerilog

RTL design

FPGA/ASIC

Timing analysis

Verilog/VHDL

ASIC/SoC integration

Python scripting

CAD tools experience

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys VCS

Siemens Questa

AMD Vivado

Xilinx toolchain

Job description

Ciklum is seeking a Senior Logic Design Engineer in Poland to advance next-generation FPGA/ASIC platforms. You will design high-performance, low-latency RTL modules with SystemVerilog and collaborate with architects, verification, software, and hardware teams in an international setting.

Responsibilities include lifecycle design, timing optimization, and IP integration, with a focus on CDC-aware, high-speed interfaces.