Partitioning Lead, Physical Design (Semiconductors) – Hybrid

Capgemini Engineering; Katowice; Hybrid; PLN 350,000 - 600,000; Full time

Benefits offered by this job

Hybrid work model

Well-being programs

Extensive training resources

Job summary

Capgemini Engineering is seeking a Physical Design expert with partitioning experience aiming to become a Lead or Tech Lead for exciting new projects. Join us as a PD Partitioning Lead to drive design cycles in cutting-edge technologies.

You will work on full-chip and block-level PD, including floorplanning, partitioning, timing planning, and ECO tasks, with potential to lead a small team. Hybrid work model in Poland is available.

Qualifications

• Extensive experience in physical design at advanced nodes (10nm and below).
• Experience with partitioning, floorplanning, power mesh distribution, clock tree, placement, routing, timing closure.
• Strong scripting in Perl/TCL/Python to develop timing-related scripts.
• Experience with sign-off tape-out closure.
• Ability to lead small teams.

Responsibilities

• Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below).
• In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route.
• Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing).
• In charge with all validation/qualification tasks: Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes.
• Be part of the overall Low Power solution development and implementation.
• Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level).
• Complete multiple design cycles of high complexity with little supervision.
• Possiblity to lead other PD Engineers.

Skills

Synthesis flow

Floorplanning

Timing closure

Perl/Python scripting

Timing analysis

EM/IR, DRC, LVS

Leadership

Partitioning experience

Tools

Makefile

Job description

Capgemini Engineering is seeking a Physical Design expert with partitioning experience aiming to become a Lead or Tech Lead for exciting new projects. Join us as a PD Partitioning Lead to drive design cycles in cutting-edge technologies.

You will work on full-chip and block-level PD, including floorplanning, partitioning, timing planning, and ECO tasks, with potential to lead a small team. Hybrid work model in Poland is available.