Partitioning Lead - Full-Chip Physical Design

Capgemini Engineering

Województwo pomorskie

Hybrid

PLN 360.000 - 600.000

Vollzeit

Vor 7 Tagen
Sei unter den ersten Bewerbenden

Eine vollständige Bewerbung in einer Minute

Maßgeschneiderter Lebenslauf und Anschreiben – versandbereit.

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Benefits dieser Stelle

Hybrid work model
Medical care with Medicover
Private life insurance
Sports card

Zusammenfassung

Capgemini Engineering is seeking a Physical Design expert with partitioning experience to become a Lead or Tech Lead on new projects. Join our global team of engineers delivering advanced design solutions for cutting-edge technologies.

You will drive PD activities from partitioning and floorplanning to timing closure, ECO tasks, and sign-off readiness, while mentoring junior PD engineers and shaping architecture for 10nm and below processes.

Qualifikationen

  • Expertise in physical design and sign-off workflows.
  • Experience in partitioning and leading small teams is a plus.
  • Strong scripting abilities with Perl/TCL/Python.
  • Excellent timing closure and DRC/LVS/ERC analysis skills.
  • Experience with sign-off tape-out closure work.
  • Experience with 10nm and below technologies is preferred.

Aufgaben

  • Lead PD activities including partitioning, timing closure, and ECO tasks.
  • Develop timing related scripts for clock skew and path analysis.
  • Coordinate with sign-off teams to ensure tape-out readiness.
  • Mentor junior PD engineers as needed.

Kenntnisse

Synthesis flow
Floorplanning
Power planning
CTS
Place & route
Timing closure
Perl/TCL/Python
EM/IR analysis
Timing STA/PTSI
Tape-out closure
Leadership

Tools

Makefile
Perl
Python
TCL

Jobbeschreibung

Capgemini Engineering is seeking a Physical Design expert with partitioning experience to become a Lead or Tech Lead on new projects. Join our global team of engineers delivering advanced design solutions for cutting-edge technologies.

You will drive PD activities from partitioning and floorplanning to timing closure, ECO tasks, and sign-off readiness, while mentoring junior PD engineers and shaping architecture for 10nm and below processes.

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