PD Partitioning Lead for Advanced SoCs - Hybrid

Capgemini Engineering; Lublin; Hybrid; PLN 260.000 - 380.000; Vollzeit

Benefits dieser Stelle

Medical care (Medicover)

Private life insurance

Sports card

Hybrid working model

Zusammenfassung

Capgemini Engineering is seeking a Physical Design expert with partitioning experience who aspires to become a Lead or Tech Lead on exciting projects. You will join as a PD Partitioning Lead, driving full-chip and block-level design activities in advanced nodes, and potentially leading small PD teams.

You will work on floorplanning, partitioning, power distribution, clock tree planning, timing closure, and ECO tasks.

Qualifikationen

• Experience in Physical Design across full-chip or block level in advanced nodes (10nm and below).
• Strong knowledge of floorplanning, CTS, placement, routing and timing closure.
• Proficiency in scripting (Perl, TCL, Python) and Makefile for automation.
• Expertise in timing STA/PTSI, sign-off closure, and physical verification.
• Ability to lead/mentoring small teams.

Aufgaben

• Own all aspects of Physical Design in full chip or block level.
• Lead deep Floorplanning, partitioning, budget, power mesh and clock tree planning.
• Manage timing analysis, ECO tasks and sign-off closure including SI/noise.
• Oversee validation: DRC, LVS, EM/IR, Antenna, ERC; fix issues.
• Contribute to Low Power solution development and implementation.
• Develop/enhance timing scripts for clock skew and IO constraints.
• Lead multiple design cycles with minimal supervision; mentor juniors.

Kenntnisse

Floorplanning

Power mesh distribution

Clock tree planning

Timing closure

Synthesis flow

TD/TVDTD (DFT) optimization

Perl scripting

Python scripting

TCL scripting

Place and route

Sign-off timing

Tools

Makefile

Perl scripting

Python scripting

TCL scripting

Jobbeschreibung

Capgemini Engineering is seeking a Physical Design expert with partitioning experience who aspires to become a Lead or Tech Lead on exciting projects. You will join as a PD Partitioning Lead, driving full-chip and block-level design activities in advanced nodes, and potentially leading small PD teams.

You will work on floorplanning, partitioning, power distribution, clock tree planning, timing closure, and ECO tasks.