Physical Design Lead - Chip Partition & Timing

Capgemini Engineering; Warszawa; Hybrid; PLN 180,000 - 240,000; Full time

Benefits offered by this job

Hybrid working model

Medicover medical care

Private life insurance

Job summary

Capgemini Engineering is seeking a Physical Design expert with partitioning experience who aspires to a Lead or Tech Lead role on forward-looking projects. You will drive full chip and block-level PD activities, including floorplanning, partitioning, timing closure, DRC/LVS/ER C, and low-power solutions, with a hybrid work arrangement.

The role emphasizes leadership potential, advanced node design, and scripting for timing and ECO tasks, offering opportunities to influence multiple design cycles

Qualifications

• Experience in Physical Design for 10nm and below nodes.
• Ability to lead/tech lead small teams.
• Strong debugging and ECO generation skills.
• Proficiency in timing closure, STA/PTSI, and signal integrity.

Responsibilities

• Lead full chip or block-level Physical Design activities.
• Perform floorplanning, partitioning, power mesh distribution, and clock tree planning.
• Conduct timing analysis and sign-off, including SI and noise considerations.
• Handle ECOs, verification (DRC/LVS/ERC), and validation tasks.
• Develop/enhance timing-related scripts for clock skew analysis and constraints.

Skills

Floorplanning

Power/clock design

Synthesis flow optimization

Sign-off timing

Timing closure

Tools

Perl

TCL

Python

Makefile

Job description

Capgemini Engineering is seeking a Physical Design expert with partitioning experience who aspires to a Lead or Tech Lead role on forward-looking projects. You will drive full chip and block-level PD activities, including floorplanning, partitioning, timing closure, DRC/LVS/ER C, and low-power solutions, with a hybrid work arrangement.

The role emphasizes leadership potential, advanced node design, and scripting for timing and ECO tasks, offering opportunities to influence multiple design cycles