Senior Standard Cell Design Engineer (Sub-3nm) – Hybrid

Arm Limited; Hinoba-an; Hybride; PHP 1 000 000 - 1 400 000; Plein temps

Avantages offerts par ce poste

Hybrid working

Equal opportunity employer

Résumé du poste

Arm is seeking a highly skilled Solutions Engineering Physical IP engineer to develop custom standard cells for sub-3nm process technologies. You will collaborate with circuit, physical, and mask design teams to optimize PPA and deliver production-quality standard cell libraries.

The role requires strong transistor-level design expertise, standard cell characterization, EDA modeling, and automation. Hybrid working arrangements are available to support performance and wellbeing.

Qualifications

• BSEE with 4+ years of circuit design or standard cell characterization experience or MSEE with 3+ years.
• Experience identifying, designing, optimizing, and verifying standard cells for PPA improvements.
• Strong understanding of MOSFET electrical characteristics, device physics, layout effects, and process variability for advanced nodes.
• Expertise in transistor-level design of static CMOS circuits including latches and flip-flops.
• Hands-on experience with standard cell characterization, EDA view generation, modeling, and QA/validation.
• Proficiency with industry-standard cell characterization tools and SPICE-level simulators.

Responsabilités

• Develop and optimize Arm custom standard cells for advanced sub-3nm process technology nodes.
• Perform standard cell characterization, modeling, and EDA view generation, ensuring generated models reflect design intent.
• Design, analyze, and verify transistor-level circuits to meet power, performance, area, and reliability requirements.
• Co-optimize circuit designs with physical design engineers to improve core- and SoC-level PPA.
• Collaborate with mask design engineers to optimize cell layouts for electrical performance and manufacturability.
• Develop and execute QA and validation methodologies across standard cell library views using various EDA tools.
• Identify opportunities to improve characterization methodologies, automation, tools, and processes across projects.
• Collaborate across circuit, physical, mask design, and methodology teams to deliver production-quality libraries.
• Analyze complex issues, develop practical solutions, and communicate conclusions to engineering stakeholders.

Connaissances

Standard cell design

Characterization & QA

Transistor-level design

MOSFET physics & variability

Scripting (Python/Perl)

EDA tools proficiency

SPICE simulations

Formation

BSEE with 4+ years of relevant circuit design and/or standard cell characterization experience

MSEE with 3+ years of relevant experience

Outils

SPICE

EDA tools

Python/Perl scripting

Description du poste

Arm is seeking a highly skilled Solutions Engineering Physical IP engineer to develop custom standard cells for sub-3nm process technologies. You will collaborate with circuit, physical, and mask design teams to optimize PPA and deliver production-quality standard cell libraries.

The role requires strong transistor-level design expertise, standard cell characterization, EDA modeling, and automation. Hybrid working arrangements are available to support performance and wellbeing.