Senior High-Speed Analog Designer — SerDes IP

Synopsys, Inc.; Hinoba-an; On-site; PHP 7,505,000 - 11,257,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced analog designer to develop multi-Gbps SerDes IP in the latest FinFET nodes.

You will create sub-blocks such as VCOs, drivers, and PLLs, and translate standards into concrete block specifications while balancing power, area, and performance. The role requires deep transistor-level design expertise, SPICE/Verilog-A modeling, and close collaboration with layout teams to minimize parasitics and ensure robust performance.

Qualifications

• Bachelor's or Master's in Electrical/Electronic Engineering with 6+ years (or 4+ with Master) of relevant work.
• Deep transistor-level circuit design experience in CMOS on advanced nodes.
• Proven experience with at least one SerDes sub-circuit (receive EQs, drivers, VCOs, PLL/DLL, ADC/DAC).
• Proficiency with SPICE simulators and corner/aging analysis.
• Working knowledge of Verilog-A for analog modeling and data capture.
• Experience with schematic entry, layout, and verification tools; layout-aware design is a plus.

Responsibilities

• Design analog sub-blocks for multi-Gbps SerDes IP including VCOs, drivers, PLLs, DLLs, ADCs, DACs, and serializers/deserializers.
• Translate SerDes standards into block-level specs balancing power, area, and performance across FinFET nodes.
• Evaluate architectures and topologies considering layout constraints and process variation.
• Oversee physical layout with layout engineers to minimize parasitics and ensure robust matching and ESD protection.
• Develop SPICE/Verilog-A verification strategies across corners and aging conditions.
• Present simulation data and design reviews to peers and customers; document design features and test plans.
• Contribute to post-silicon characterization and propose design updates based on results.

Skills

Transistor-level design

SerDes sub-circuits

SPICE simulations

Verilog-A modeling

Schematic entry & layout

Scripting (TCL, Python, MATLAB)

CMOS process knowledge

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Verilog-A

SPICE/Analog simulators

Layout tools

Job description

Synopsys, Inc. is seeking an experienced analog designer to develop multi-Gbps SerDes IP in the latest FinFET nodes.

You will create sub-blocks such as VCOs, drivers, and PLLs, and translate standards into concrete block specifications while balancing power, area, and performance. The role requires deep transistor-level design expertise, SPICE/Verilog-A modeling, and close collaboration with layout teams to minimize parasitics and ensure robust performance.