Staff High-Speed Analog Designer

Synopsys, Inc.; Hinoba-an; On-site; PHP 7,505,000 - 11,257,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced analog designer to develop multi-Gbps SerDes IP in the latest FinFET nodes.

You will create sub-blocks such as VCOs, drivers, and PLLs, and translate standards into concrete block specifications while balancing power, area, and performance. The role requires deep transistor-level design expertise, SPICE/Verilog-A modeling, and close collaboration with layout teams to minimize parasitics and ensure robust performance.

Qualifications

• Bachelor's or Master's in Electrical/Electronic Engineering with 6+ years (or 4+ with Master) of relevant work.
• Deep transistor-level circuit design experience in CMOS on advanced nodes.
• Proven experience with at least one SerDes sub-circuit (receive EQs, drivers, VCOs, PLL/DLL, ADC/DAC).
• Proficiency with SPICE simulators and corner/aging analysis.
• Working knowledge of Verilog-A for analog modeling and data capture.
• Experience with schematic entry, layout, and verification tools; layout-aware design is a plus.

Responsibilities

• Design analog sub-blocks for multi-Gbps SerDes IP including VCOs, drivers, PLLs, DLLs, ADCs, DACs, and serializers/deserializers.
• Translate SerDes standards into block-level specs balancing power, area, and performance across FinFET nodes.
• Evaluate architectures and topologies considering layout constraints and process variation.
• Oversee physical layout with layout engineers to minimize parasitics and ensure robust matching and ESD protection.
• Develop SPICE/Verilog-A verification strategies across corners and aging conditions.
• Present simulation data and design reviews to peers and customers; document design features and test plans.
• Contribute to post-silicon characterization and propose design updates based on results.

Skills

Transistor-level design

SerDes sub-circuits

SPICE simulations

Verilog-A modeling

Schematic entry & layout

Scripting (TCL, Python, MATLAB)

CMOS process knowledge

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Verilog-A

SPICE/Analog simulators

Layout tools

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years designing analog circuits that need to hit power, area, and performance targets in unforgiving process nodes, and you have learned that the best architectures are the ones you can actually close in layout. You think in tradeoffs, not ideals. When you read a SerDes standard, you see the circuit blocks underneath it, and you already have two or three candidate topologies sketched out before the spec is finalized.

You are comfortable moving between transistor-level design and system-level thinking. You know that a VCO phase noise spec is meaningless without understanding the PLL loop dynamics, and you can explain that relationship to a digital designer or a customer without losing the thread. Layout is not something that happens after you finish the schematic. It is part of your design process, and you have strong opinions about how parasitics, stress, and mismatch should shape your floorplan from day one.

You do not wait for perfect simulation corners to declare a design done. You run the right simulations, interpret the data, and make calls. At Synopsys, you will work on multi-Gbps NRZ and PAM4 SerDes IP in the latest FinFET nodes, alongside a team that takes analog design seriously and has the tools and support to back it up.

What You'll Be Doing

• Design and develop analog sub-blocks for multi-Gbps NRZ and PAM4 SerDes IP, including equalizers, samplers, drivers, VCOs, PLLs, DLLs, ADCs, DACs, and serializers/deserializers
• Review SerDes standards and translate them into block-level specifications that balance power, area, and performance across the latest FinFET process nodes
• Identify and refine circuit architectures, evaluating multiple topologies and making design decisions that account for layout constraints, process variation, and reliability
• Oversee physical layout implementation, working closely with layout engineers to minimize parasitics, manage device stress, and ensure robust matching and ESD protection
• Develop simulation strategies using SPICE simulators, Verilog-A behavioral models, and scripting (TCL, Perl, Python, MATLAB) to verify circuit performance across corners and conditions
• Present simulation data and design reviews to peers and customers, documenting design features, test plans, and tradeoffs
• Consult on post-silicon characterization and propose design updates based on electrical test results

The Impact You Will Have

• Your circuit architectures will directly shape the power, area, and performance of SerDes IP that ships in high-volume semiconductor products
• The design strategies and verification methods you develop will become reference flows for the analog team, raising the bar for quality and efficiency
• Your layout oversight will reduce post-silicon surprises, cutting time to market and improving first-pass silicon success rates
• The simulation data and documentation you produce will enable faster customer adoption and smoother integration of SerDes IP into SoC designs
• Your collaboration with digital designers and software teams will strengthen cross-functional design practices and improve overall IP robustness
• The design-for-reliability and ESD techniques you implement will extend product lifetime and reduce field failures
• Your contributions to post-silicon debug will close the loop between design intent and measured performance, driving continuous improvement

What You'll Need

• Bachelor's degree with 6+ years of relevant experience or Master's degree with 4+ years of relevant experience in Electrical Engineering, Computer Engineering, or a related field
• Deep transistor-level circuit design experience with strong CMOS design fundamentals and hands-on work in advanced process nodes
• Detailed design experience with at least one SerDes sub-circuit (receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, VCO, phase mixer, DLL, PLL, bandgap reference, ADC, DAC) and familiarity with several others
• Proficiency with SPICE simulators and simulation methods, including corner analysis, Monte Carlo, and aging simulations
• Working knowledge of Verilog-A for analog behavioral modeling, simulation control, and data capture
• Experience with schematic entry, physical layout, and design verification tools, hands-on layout experience with high-speed circuits is a plus
• Familiarity with scripting languages such as TCL, Perl, Python, C, or MATLAB for automation and data analysis is desired

Who You Are

• You can look at a block spec and quickly sketch two or three circuit topologies, then articulate the tradeoffs between them in a design review without needing slides
• You treat layout as part of the design, not an afterthought, and you know how to work with layout engineers to get matching, parasitics, and floorplanning right the first time
• You are comfortable presenting simulation data to customers and peers, defending your design choices, and adjusting your approach when the data tells you to
• You know the difference between a simulation that gives you confidence and one that just checks a box, and you design your verification strategy accordingly
• You can move between deep circuit-level work and system-level discussions with digital designers, understanding how your block fits into the larger SerDes architecture
• You document your work clearly, not because someone asked you to, but because you know the next person (or future you) will need to understand what you built and why

The Team You'll Be Part Of

You will join a growing analog and mixed-signal R&D team focused on high-speed SerDes IP development in the latest FinFET process nodes. The team works cross-functionally with digital designers, software engineers, and a dedicated CAD team that supports custom in-house tools alongside a full suite of industry-standard IC design tools.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.