DFT Engineer — AI Accelerator SoC & Test Lead

IC Resources Recruitment; London; On-site; NOK 761,000 - 1,141,000; Full time

Benefits offered by this job

Innovative AI silicon

Collaborative culture

Full ASIC lifecycle exposure

Cross-disciplinary collaboration

Job summary

IC Resources Recruitment is seeking a DFT Engineer in London to join a British AI company pushing next-generation AI hardware. You will design-for-test architectures for multi-core AI accelerator SoCs and integrate DFT methodologies into the ASIC flow.

The role covers ATPG, MBIST, scan chain, memory BIST, and automation scripting to improve test efficiency. You will collaborate with Physical Design and Product teams and contribute to silicon bring-up and production testing.

Qualifications

• Bachelor's degree in Electronic, Computer or Computer Engineering or related field.
• Experience in design-for-test (DFT), digital IC design, or ASIC development.
• Solid understanding of scan architecture, ATPG, MBIST and digital testing methodologies.
• Familiarity with industry-standard EDA tools and scripting languages (Python, Tcl).

Responsibilities

• Contribute to the design-for-test (DFT) architecture of a complex multi-core AI accelerator SoC.
• Integrate DFT methodologies and tools into the ASIC design process.
• Implement scan insertion, scan compression, and related test logic.
• Generate, analyze ATPG patterns and ensure structural fault coverage.
• Support MBIST for large embedded memory arrays.
• Collaborate with Physical Design teams to ensure scan chain implementation and timing closure.
• Develop scripting and automation solutions to enhance DFT efficiency.
• Assist in silicon bring-up, manufacturing testing and post-silicon debugging.
• Work with Product and Test Engineering teams to enable ATE bring-up and production testing.

Skills

DFT

ASIC development

ATPG

MBIST

EDA tools

Python

Tcl

Scan architecture

Education

Bachelor's degree in Electronic/Computer Engineering

Tools

Industry-standard EDA tools

Job description

IC Resources Recruitment is seeking a DFT Engineer in London to join a British AI company pushing next-generation AI hardware. You will design-for-test architectures for multi-core AI accelerator SoCs and integrate DFT methodologies into the ASIC flow.

The role covers ATPG, MBIST, scan chain, memory BIST, and automation scripting to improve test efficiency. You will collaborate with Physical Design and Product teams and contribute to silicon bring-up and production testing.