Senior Digital IC Designer

IC Resources; Oslo; On-site; NOK 700,000 - 900,000; Full time

Job summary

IC Resources is looking for a highly skilled Staff Digital Design Engineer to join their design team based in Oslo, Norway. This role offers the opportunity to work on innovative projects focused on CMOS Image Sensors. The successful candidate will have extensive experience in ASIC design and verification, as well as the ability to mentor junior team members.

Applicants from outside Norway are encouraged, even if prior experience in image sensor design is not a strict requirement.

Qualifications

• Minimum of 7+ years of experience in digital design.
• Expertise in ASIC design and verification.
• Experience with chip development cycle and low-power design.

Responsibilities

• Designing and verifying digital IP for CMOS Image Sensors (CIS).
• Defining chip-level architecture and specifications.
• Leading full-chip integration and verification efforts.

Skills

RTL design and verification

Logic synthesis

Static timing analysis

Collaborative teamwork

Education

Master’s degree in Electrical Engineering

Job description

We are seeking a highly skilled and experienced Staff Digital Design Engineer to join our clients IC design team in Norway. This is an exciting opportunity to contribute to cutting-edge projects in the field of digital design for CMOS Image Sensors (CIS). The ideal candidate will have a strong background in ASIC design and verification, a passion for innovation, and the ability to mentor junior team members while collaborating across functional areas.

International applications are welcome! Previous experience in image sensor design is not essential.

Responsibilities

As a Staff Digital Design Engineer, your key responsibilities will include:

• Designing and verifying digital IP for CMOS Image Sensors (CIS).
• Defining chip-level architecture with a focus on power, performance, and area trade-offs, and building top-level and module specifications.
• Performing logic synthesis and collaborating with the backend team for floor planning, static timing analysis (STA), and design-for-test (DFT).
• Driving innovation and continuous improvement in the design flow.
• Mentoring and guiding junior team members.
• Participating in project planning and progress tracking to ensure timely delivery.
• Leading full-chip integration and verification efforts.
• Supporting silicon bring-up, validation, and debugging activities.

Qualifications

To be successful in this role, you should meet the following qualifications:

• A minimum of a Master’s degree in Electrical Engineering (MSEE) with at least 7+ years of experience in digital design.
• Expertise in RTL design and verification for ASICs.
• Proven experience in handling logic synthesis and static timing analysis across multiple projects.
• Comprehensive knowledge of the chip development cycle, including design specification, architecture definition, low‑power design, tape‑out, and chip validation/debug.
• Technical leadership experience is highly desirable.
• Familiarity with ASIL, DFT, and image processing/DSP is a plus.
• Excellent command of English as a working language.
• Strong ability to work collaboratively with cross‑functional teams.