Senior Digital Verification Engineer – Crypto & Security (Remote)

NXP Semiconductors NV; Eindhoven; Hybrid; EUR 80,000 - 110,000; Full time

Job summary

NXP Semiconductors is expanding its Crypto & Security Competence Centre in the Netherlands. We seek a Digital Verification Engineer to drive AI-assisted verification of PQC and security IP and to architect scalable SystemVerilog/UVM environments.

You will mentor peers, apply MDV methodologies, and collaborate with design and architecture teams to ensure high-quality silicon delivery. Remote/hybrid options apply.

Qualifications

• Strong hands-on experience with SystemVerilog for testbench development and verification.
• Proven expertise in UVM (Universal Verification Methodology).
• Experience with constrained random verification and coverage-driven approaches.

Responsibilities

• Lead verification of PQC and security IP with complex design challenges.
• Define verification strategy leveraging AI and automation to boost quality.
• Architect and scale SystemVerilog/UVM environments for IP and subsystems.
• Champion constrained random and MDV verification methodologies.
• Own coverage closure using data-driven insights for sign-off.
• Develop SVA for protocol checking and early defect detection.
• Collaborate with design teams to influence verification early.
• Mentor engineers to maintain a high-performing team culture.

Skills

SystemVerilog testbench

UVM expertise

Constrained Random Verification

Metrics-Driven Verification

SystemVerilog Assertions

Debugging in simulations

Formal Verification (advantage)

Education

BSc./MSc Electronics or Electrical Engineering

Tools

SystemVerilog

UVM components (sequences, drivers, monitors, scoreboards)

Constrained Random Verification

SVA tooling

Job description

NXP Semiconductors is expanding its Crypto & Security Competence Centre in the Netherlands. We seek a Digital Verification Engineer to drive AI-assisted verification of PQC and security IP and to architect scalable SystemVerilog/UVM environments.

You will mentor peers, apply MDV methodologies, and collaborate with design and architecture teams to ensure high-quality silicon delivery. Remote/hybrid options apply.