Senior Digital Verification Engineer, Crypto & Security

NXP Semiconductors NV; Eindhoven; Ibrido; EUR 80.000 - 110.000; Tempo pieno

Descrizione del lavoro

NXP Semiconductors is expanding its Crypto & Security Competence Centre in the Netherlands. We seek a Digital Verification Engineer to drive AI-assisted verification of PQC and security IP and to architect scalable SystemVerilog/UVM environments.

You will mentor peers, apply MDV methodologies, and collaborate with design and architecture teams to ensure high-quality silicon delivery. Remote/hybrid options apply.

Competenze

• Strong hands-on experience with SystemVerilog for testbench development and verification.
• Proven expertise in UVM (Universal Verification Methodology).
• Experience with constrained random verification and coverage-driven approaches.

Mansioni

• Lead verification of PQC and security IP with complex design challenges.
• Define verification strategy leveraging AI and automation to boost quality.
• Architect and scale SystemVerilog/UVM environments for IP and subsystems.
• Champion constrained random and MDV verification methodologies.
• Own coverage closure using data-driven insights for sign-off.
• Develop SVA for protocol checking and early defect detection.
• Collaborate with design teams to influence verification early.
• Mentor engineers to maintain a high-performing team culture.

Conoscenze

SystemVerilog testbench

UVM expertise

Constrained Random Verification

Metrics-Driven Verification

SystemVerilog Assertions

Debugging in simulations

Formal Verification (advantage)

Formazione

BSc./MSc Electronics or Electrical Engineering

Strumenti

SystemVerilog

UVM components (sequences, drivers, monitors, scoreboards)

Constrained Random Verification

SVA tooling

Descrizione del lavoro

We Are Actively Expanding The Crypto & Security Competence Centre (CCC&S) At NXP And We Have New Opportunities In Our Team For Digital Verification Engineers Working On Next-generation Security Technologies Such As

• Post-Quantum Cryptography (PQC) IP
• Secure SoC subsystems, including next-generation roots of trust
• High-assurance cryptographic accelerators for future platforms

At CCC&S, we are also driving a significant transformation in how hardware is designed and verified by integrating AI directly into IC design and verification flows. The role is blended with traditional verification methods whilst the AI agents are being developed.

Driven Verification – What You’ll Be Part Of

In this role, you will contribute to a step-change in verification capability through:

• AI-driven verification automation – reducing regression effort while maintaining full coverage
• Intelligent debug and analysis – accelerating bug discovery and root-cause identification
• Automated test and vPlan generation – improving consistency and reducing human error

We Are Also Actively Developing Advanced Capabilities Including

• AI-assisted RTL understanding and test explanation
• Conversational debug interfaces for waveform and design interaction
• AI-driven coverage closure and test prioritization

This is not a future vision—this transformation is already underway within CCC&S workflows.

What You’ll Be Doing

As a key member of our growing team, you will:

• Lead the verification of advanced PQC and security IP, tackling complex, security-focused design challenges
• Define and drive verification strategy, leveraging AI and automation to enhance productivity and quality
• Architect and scale SystemVerilog/UVM verification environments for IP and subsystem-level validation
• Champion Constrained Random and Metrics-Driven Verification (MDV) methodologies
• Own and drive coverage closure, using data-driven insights for high-confidence sign-off
• Develop SystemVerilog Assertions (SVA) for protocol checking and early defect detection
• Collaborate closely with design and architecture teams to influence verification from early stages
• Mentor and support engineers, contributing to a high-performing and forward-looking team culture

Why This Role Stands Out

• Work on cutting-edge cryptography technologies critical to future cybersecurity
• Help define how AI transforms verification workflows and methodologies
• Join a growing organisation where your input shapes tools, processes, and technical direction
• Take ownership of high-visibility, complex projects from concept to silicon

Your Profile

• BSc., or MSc., degree in Electronics or Electrical Engineering.
• Strong hands-on experience with SystemVerilog for testbench development and verification.
• Proven expertise in UVM (Universal Verification Methodology), including component creation, sequences, drivers, monitors, and scoreboards.
• Solid understanding and practical use of Constrained Random Verification techniques.
• Experience with Metrics‑Driven Verification, including functional coverage and verification planning.
• Ability to write SystemVerilog Assertions (SVA) for protocol and design checking.
• Demonstrated success in achieving Coverage Closure across functional and code coverage metrics.
• Experience analysing coverage results and refining test strategies to close gaps.
• Strong debugging skills across simulations and complex verification environments.
• Knowledge of Formal Verification methods would be advantageous.

• Remote / Hybrid working is applicable to this position.

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