Senior Digital Design Engineer — RTL/Verilog & Timing

SiTime Corp.; Rijswijk; On-site; EUR 70,000 - 100,000; Full time

Job summary

SiTime Corporation seeks a Senior Logic Design Engineer to join our digital design team. You will develop RTL from PRD, implement Verilog/SystemVerilog, and create test benches to validate complex timing and functionality in high-precision MEMS timing products.

You will analyze STA reports, optimize timing/area/power tradeoffs, and collaborate with analog, verification, backend, and test teams to ensure first-time silicon success across multiple projects.

Qualifications

• Master’s degree in electrical engineering with 5 years of industry experience.
• Excellent verbal and written communication skills in English.
• Proficient in Verilog and SystemVerilog.
• Experience in RTL design, synthesis, timing constraints, and STA.
• Scripting in Perl/Tcl/Python.

Responsibilities

• Develop micro-architecture specifications from PRD.
• Create RTL designs using Verilog/SystemVerilog.
• Develop standalone test benches to verify RTL.
• Write and verify SystemVerilog Assertions (SVA).
• Write timing constraints for synthesis and place-and-route tools.
• Run industry-standard synthesis tools and fix timing problems.
• Cross-functional interactions with analog, verification, backend, system, and test teams.
• Post-Si bring-up, validation, and debugging.

Skills

Verilog

SystemVerilog

RTL design

Scripting (Python)

STA analysis

Education

Master’s in Electrical Engineering

Tools

Genus

Design Compiler

PrimeTime

Job description

SiTime Corporation seeks a Senior Logic Design Engineer to join our digital design team. You will develop RTL from PRD, implement Verilog/SystemVerilog, and create test benches to validate complex timing and functionality in high-precision MEMS timing products.

You will analyze STA reports, optimize timing/area/power tradeoffs, and collaborate with analog, verification, backend, and test teams to ensure first-time silicon success across multiple projects.