Sr. Engineer, Verifications

SiTime Corp.; Rijswijk; On-site; EUR 90,000 - 130,000; Full time

Job summary

SiTime Corp. in the Netherlands is seeking a Senior Verification Engineer to join a team developing MEMS timing ICs. You will contribute to SV-RNM models, UVM-based verification environments and SystemVerilog assertions.

The role emphasizes collaboration with design, test and verification teams across dispersed sites, strong English communication, and hands-on debugging of complex analog/mixed-signal verification flows.

Qualifications

• 5+ years of verification in semiconductor industry.
• Strong SystemVerilog/ UVM experience.
• Experience with SystemVerilog Assertions.
• Proficient in scripting languages (Perl / Python).
• Ability to communicate with dispersed teams.

Responsibilities

• Develop SV-RNM models for analog and mixed-signal circuits.
• Develop verification plans from specifications.
• Create UVM-based verification environments (scoreboards, monitors, sequencers).
• Develop digital-top verification in SystemVerilog.
• Define and write SVA, coverages and covergroups.
• Run simulations and debug results.
• Review verification results for Tape-out sign-off.
• Collaborate with design/test/verification teams to share information.

Skills

SystemVerilog

UVM

SVA

C++

Verilog

OOP

Education

MS in electrical/computer engineering

Tools

Cadence Virtuoso

Job description

About SiTime

SiTime is the Precision Timing company. Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com.

Job Summary

As a Senior Verification Engineer, you will be part of a team developing MEMS timing ICs. It is not necessary to meet all job requirements to be a qualified candidate for the position.

Responsibilities

• Developing SV-RNM models for both analog and mixed-signal circuits
• Developing verification plan from chip or block specifications
• Developing UVM-based verification environment (scoreboards, monitors, sequencers, etc.)
• Developing digital-top verification in System Verilog
• Defining and writing System Verilog Assertions (SVA)
• Defining and writing functional coverages and covergroups
• Running simulations and debugging simulation results
• Reviewing verification results for Tape-out sign-off
• Communicating with stakeholders (design/test/verification) to facilitate teamwork and efficient sharing of information and exchange of ideas

Minimum Requirements

• MS (BS) degree in electrical/computer engineering or related fields with 5 (8) years of work experience doing verification in the semiconductor industry
• Good verbal and written communication skills in English
• Proficient in SystemVerilog and SystemVerilog OOP
• Fluency in utilizing scripting languages such as Perl / Python
• Proficient (through work experience) in verification using UVM
• Strong experience writing SystemVerilog Assertions (SVA)
• Understanding of Analog schematic and experience with Cadence Virtuoso
• Basic understanding of digital design using Verilog
• Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital design and analog design engineers
• Ability to work independently and drive solutions to challenging problems

Desired Qualification

• Experience with generating functional models for analog blocks using SystemVerilog RNM, Wreal (V-AMS), or similar techniques
• Experience with UVM-AMS methodology
• Solid experience with Formal Property Verification (FPV)
• Programming experience writing OOP code in C++
• Excellent written and verbal communication skills in English
• Experience with performing analog mixed-signal verification
• Proven track record in working well with others in fast-paced and collaborative work environment
• Knowledge of analog design
• Knowledge of synthesizable digital design
• Experience working on verification of datapath designs including filters

The actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.

SiTime compensation packages includes base salary, bonus based on achieving your innovation goals and equity.

SiTime is an Equal Opportunity Employer. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program.

Learn More about SiTime

• Innovation on Top – Philosophies of Innovation with Rajesh Vashist
• Fabrication Knowledge – An Interview with Rajesh Vashist
• SiTime Corporation – YouTube