Senior Verification Engineer – MEMS Timing ICs (UVM)

SiTime Corp.; Rijswijk; On-site; EUR 90,000 - 130,000; Full time

Job summary

SiTime Corp. in the Netherlands is seeking a Senior Verification Engineer to join a team developing MEMS timing ICs. You will contribute to SV-RNM models, UVM-based verification environments and SystemVerilog assertions.

The role emphasizes collaboration with design, test and verification teams across dispersed sites, strong English communication, and hands-on debugging of complex analog/mixed-signal verification flows.

Qualifications

• 5+ years of verification in semiconductor industry.
• Strong SystemVerilog/ UVM experience.
• Experience with SystemVerilog Assertions.
• Proficient in scripting languages (Perl / Python).
• Ability to communicate with dispersed teams.

Responsibilities

• Develop SV-RNM models for analog and mixed-signal circuits.
• Develop verification plans from specifications.
• Create UVM-based verification environments (scoreboards, monitors, sequencers).
• Develop digital-top verification in SystemVerilog.
• Define and write SVA, coverages and covergroups.
• Run simulations and debug results.
• Review verification results for Tape-out sign-off.
• Collaborate with design/test/verification teams to share information.

Skills

SystemVerilog

UVM

SVA

C++

Verilog

OOP

Education

MS in electrical/computer engineering

Tools

Cadence Virtuoso

Job description

SiTime Corp. in the Netherlands is seeking a Senior Verification Engineer to join a team developing MEMS timing ICs. You will contribute to SV-RNM models, UVM-based verification environments and SystemVerilog assertions.

The role emphasizes collaboration with design, test and verification teams across dispersed sites, strong English communication, and hands-on debugging of complex analog/mixed-signal verification flows.