RTL Design Engineer - AI IP for Wearables

Snap; Eindhoven; On-site; EUR 90,000 - 130,000; Full time

Benefits offered by this job

Paid parental leave

Medical coverage

Mental health support

Equity/long-term incentives

Job summary

Snap is seeking a RTL Design Engineer for its hardware IP design team. You will design and implement state-of-the-art RTL IPs for wearable devices, contributing to hardware launches at Snap and Specs Inc.

The role involves architecture definition, RTL design, synthesis, and power optimization, with close collaboration with verification and R&D teams. The ideal candidate has 5+ years in RTL design/verification, strong Verilog/SystemVerilog/VHDL skills, and experience with Python/C++.

Qualifications

• MSc degree in electrical engineering or related field.
• 5+ years of RTL hardware design and/or verification.
• Experience with AI/ML hardware is a plus.

Responsibilities

• Design and implement RTL IPs for wearable devices used in hardware launches.
• Define micro-architecture, RTL design, gate-level synthesis, and PPA optimization.
• Debug designs in collaboration with the verification team.
• Develop and maintain flows for regression tests, synthesis, linting, and power analysis.
• Collaborate with NN/AI teams and other R&D groups.

Skills

Verilog

SystemVerilog

VHDL

DfX

Python

C/C++

English

Problem solving

Education

MSc in Electrical Engineering

Tools

Git

Job description

Snap is seeking a RTL Design Engineer for its hardware IP design team. You will design and implement state-of-the-art RTL IPs for wearable devices, contributing to hardware launches at Snap and Specs Inc.

The role involves architecture definition, RTL design, synthesis, and power optimization, with close collaboration with verification and R&D teams. The ideal candidate has 5+ years in RTL design/verification, strong Verilog/SystemVerilog/VHDL skills, and experience with Python/C++.