AI-Driven RTL Design Engineer for Wearables

Snap Inc.; Eindhoven; Hybrid; EUR 70,000 - 110,000; Full time

Benefits offered by this job

Paid parental leave

Medical coverage

Emotional and mental health support

Competitive compensation

Job summary

Snap Inc. is seeking an experienced RTL Design Engineer to join our Hardware IP design team. You will micro-architect, design, implement and debug state-of-the-art AI IPs for wearable devices, working closely with architecture, verification and other R&D groups.

You will develop flows for regression tests, synthesis, linting and power analysis, and contribute to coverage closure while documenting designs clearly. A MSc in electrical engineering and 5+ years RTL experience are expected.

Qualifications

• MSc degree in related field such as electrical engineering or equivalent years of experience.
• 5+ years of experience in RTL hardware design and/or verification.
• Experience with RTL design methodologies and languages (Verilog, SystemVerilog, VHDL).
• Experience with DfX, testability, MBIST+Repair, yield enhancement, test patterns, memory ECC, and debug infrastructure.

Responsibilities

• Design and implement our RTL IPs for wearables and hardware at Snap.
• Micro-architecting, RTL design, gate-level synthesis, and PPA optimisation.
• Debugging the design with the verification team.
• Develop and maintain flows for regression tests, synthesis, linting, and power analysis.
• Analyse code coverage and provide feedback to verification for coverage closure.
• Collaborate with R&D teams on neural network design, AI compilers, and OS.
• Author clear and comprehensive documentation.

Skills

Verilog

SystemVerilog

VHDL

C/C++

Python

Debugging

Documentation

Git

Education

MSc in electrical engineering

Tools

MBIST tools

Synthesis tools

Power analysis tools

Regression flows

Job description

Snap Inc. is seeking an experienced RTL Design Engineer to join our Hardware IP design team. You will micro-architect, design, implement and debug state-of-the-art AI IPs for wearable devices, working closely with architecture, verification and other R&D groups.

You will develop flows for regression tests, synthesis, linting and power analysis, and contribute to coverage closure while documenting designs clearly. A MSc in electrical engineering and 5+ years RTL experience are expected.