Quantum-Scale Digital Verification Engineer

Connect AI; Delft; On-site; EUR 70,000 - 110,000; Full time

Job summary

Connect AI in Delft is seeking a Digital Verification Engineer to own verification activities and shape the verification strategy for complex digital hardware. You will design reusable SystemVerilog/UVM environments, develop constrained-random tests and coverage models, and automate workflows with Python.

You will collaborate closely with RTL, FPGA, firmware and hardware engineers to identify and resolve issues early, driving quality and reliability in advanced quantum-enabled hardware systems.

Qualifications

• 4+ years of commercial ASIC/FPGA digital verification experience.

Responsibilities

• Own digital verification activities from planning and testbench architecture through coverage closure.
• Design and develop reusable SystemVerilog/UVM verification environments, including agents, drivers, monitors, sequences and scoreboards.
• Build constrained-random tests and SystemVerilog assertions to uncover design issues.
• Develop and maintain functional and code coverage models, regressions and verification automation.
• Use Python to improve workflows, testing efficiency and verification infrastructure.
• Collaborate with RTL, FPGA, firmware and hardware engineers to identify and resolve issues early.
• Contribute to continuous improvements in verification methodology and engineering quality.

Skills

SystemVerilog

UVM

Python

Constrained-random

Assertions

Code coverage

Automation

Tools

Synopsys VCS

Cadence Xcelium

Job description

Connect AI in Delft is seeking a Digital Verification Engineer to own verification activities and shape the verification strategy for complex digital hardware. You will design reusable SystemVerilog/UVM environments, develop constrained-random tests and coverage models, and automate workflows with Python.

You will collaborate closely with RTL, FPGA, firmware and hardware engineers to identify and resolve issues early, driving quality and reliability in advanced quantum-enabled hardware systems.