FPGA Engineer

Intellectual Capital Resources Ltd; Zuid-Holland; On-site; EUR 80,000 - 110,000; Full time

Job summary

Intellectual Capital Resources Ltd in Delft seeks a Senior FPGA Engineer to join a quantum computing initiative. You will help build a distributed FPGA architecture to control and read out qubits with nanosecond synchronisation, developing RTL in VHDL, self-checking testbenches, and contributing to UVM environments.

Requirements include 5+ years FPGA design in R&D, strong VHDL RTL, experience with Xilinx Vivado or Intel Quartus, QuestaSim, AXI/Avalon, Python/TCL/Shell, and Git.

Qualifications

• 5+ years FPGA design experience in an R&D environment.
• Strong RTL development using VHDL.
• Experience with Xilinx Vivado or Intel Quartus.
• Strong module-level verification experience.
• Knowledge of simulation tools such as QuestaSim.
• Understanding of processor and bus architectures including AXI or Avalon.
• Scripting experience with Python, TCL or Shell.
• Experience with Git-based development.
• Experience with Zynq, UltraScale+, RFSoC, SystemVerilog, UVM is advantageous.

Responsibilities

• Develop RTL in VHDL and self-checking testbenches.
• Contribute to wider UVM environments and FPGA architectures.
• Collaborate with FPGA, embedded software, electronics and science teams.
• Take ownership of complex design problems and influence architecture.

Job description

Senior FPGA Engineer - Delft - Quantum Computing

Help solve the hardware challenges involved in controlling quantum computers at industrial scale. We are supporting a quantum technology company developing advanced control systems used by research and engineering teams around the world. They are looking for a Senior FPGA Engineer to strengthen their digital design team in Delft.

At the heart of the position is a distributed FPGA architecture capable of controlling and reading out large numbers of qubits with nanosecond-level synchronisation. You'll take ownership of complex design problems, influence architectural decisions, and collaborate with FPGA, embedded software, electronics, and scientific teams.

From interpreting requirements through to verification, you'll develop RTL in VHDL, create self-checking testbenches, contribute to wider UVM environments, and help continuously improve FPGA architectures and engineering processes.

• 5+ years of FPGA design experience within an R&D environment
• Strong RTL development using VHDL
• Experience with Xilinx Vivado or Intel Quartus
• Strong module-level verification experience
• Knowledge of simulation tools such as QuestaSim
• Understanding of processor and bus architectures including AXI or Avalon
• Scripting experience with Python, TCL or Shell
• Experience with Git-based development
• Experience with Zynq, UltraScale+, RFSoC, SystemVerilog, UVM, DSP, timing closure, C/C++, Linux, or microarchitecture design would be advantageous.