Digital Verification Engineer

Connect AI; Delft; On-site; EUR 70,000 - 110,000; Full time

Job summary

Connect AI in Delft is seeking a Digital Verification Engineer to own verification activities and shape the verification strategy for complex digital hardware. You will design reusable SystemVerilog/UVM environments, develop constrained-random tests and coverage models, and automate workflows with Python.

You will collaborate closely with RTL, FPGA, firmware and hardware engineers to identify and resolve issues early, driving quality and reliability in advanced quantum-enabled hardware systems.

Qualifications

• 4+ years of commercial ASIC/FPGA digital verification experience.

Responsibilities

• Own digital verification activities from planning and testbench architecture through coverage closure.
• Design and develop reusable SystemVerilog/UVM verification environments, including agents, drivers, monitors, sequences and scoreboards.
• Build constrained-random tests and SystemVerilog assertions to uncover design issues.
• Develop and maintain functional and code coverage models, regressions and verification automation.
• Use Python to improve workflows, testing efficiency and verification infrastructure.
• Collaborate with RTL, FPGA, firmware and hardware engineers to identify and resolve issues early.
• Contribute to continuous improvements in verification methodology and engineering quality.

Skills

SystemVerilog

UVM

Python

Constrained-random

Assertions

Code coverage

Automation

Tools

Synopsys VCS

Cadence Xcelium

Job description

Help engineer the technology that will make quantum computing possible at scale.

I'm partnering with an ambitious, highly innovative deep-tech company in Delft that's developing sophisticated hardware at the forefront of quantum technology.

We're looking for a Digital Verification Engineer who enjoys solving complex engineering challenges, takes genuine ownership of verification quality, and wants to see their work contribute to cutting-edge physical technology.

This isn't a role where you'll simply maintain existing testbenches. You'll have the opportunity to influence verification strategy, develop robust environments, and work alongside talented digital, FPGA and hardware engineers.

The opportunity

You’ll play a key role in ensuring the reliability and performance of complex digital hardware systems.

Your responsibilities will include:

• Own digital verification activities from initial planning and testbench architecture through to coverage closure.
• Design and develop reusable SystemVerilog/UVM verification environments, including agents, drivers, monitors, sequences and scoreboards.
• Build sophisticated constrained-random tests and SystemVerilog assertions to uncover challenging design issues.
• Develop and maintain functional and code coverage models, regressions and verification automation.
• Use Python to improve workflows, testing efficiency and verification infrastructure.
• Collaborate closely with RTL, FPGA, firmware and hardware engineers to identify and resolve issues early.
• Contribute to continuous improvements in verification methodology and engineering quality.

What we're looking for

You’ll ideally bring:

• 4+ years of commercial ASIC/FPGA digital verification experience.
• Strong, hands‑on expertise in SystemVerilog and UVM.
• Experience independently developing and maintaining reusable UVM testbenches.
• A solid understanding of constrained‑random verification, assertions and functional/code coverage.
• Strong Python programming and automation skills.
• Experience with professional simulation and debugging tools, such as Synopsys VCS or Cadence Xcelium.
• Familiarity with RTL design, digital hardware architectures and verification best practices.

Bonus points for: VHDL, AXI/Avalon protocols, cocotb, PyUVM, CI/CD integration or hands‑on FPGA/hardware validation experience.

Why this opportunity stands out

Genuine engineering ownership. You’ll help shape how verification is approached rather than simply follow a predefined process.

Technology with real ambition. Work on sophisticated systems supporting the advancement of quantum computing.

The right technical environment. Collaborate with specialist engineers across digital design, software, electronics and hardware.

A chance to make your mark. Your work will directly contribute to the quality, reliability and evolution of complex engineering products.

Interested?

If you’re an experienced SystemVerilog/UVM verification engineer who’s curious about taking your expertise into one of the most exciting areas of deep‑tech engineering, I’d love to speak with you.

You don't need previous quantum computing experience — what matters is your verification expertise, engineering mindset and appetite for solving difficult technical problems.

Even if you’re not actively looking, I’m happy to share more about the engineering challenges, team and opportunity.

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