Digital Verification Engineer

microTECH Global Limited; Netherlands; On-site; EUR 70,000 - 100,000; Full time

Job summary

A leading technology firm is seeking a Senior IC Digital Verification Engineer to lead the development of Digital Verification frameworks for complex digital and mixed-signal ICs. The ideal candidate will have over 5 years of RTL and Gate-Level Verification experience, proficiency in UVM and System Verilog, and excellent leadership skills. This position offers opportunities to work with cutting-edge technologies. Preferred location is in the Netherlands, with options to work remotely.

Qualifications

• 5+ years of strong experience in both RTL and Gate-Level Verification.
• Proficient in UVM and System Verilog.
• Excellent scripting skills for automation tasks.

Responsibilities

• Define and lead the development of Digital Verification framework.
• Develop and document VIPs standardization.
• Lead and supervise Digital Verification tasks across multiple projects.

Skills

Digital Verification Industry Languages

Leadership

Scripting skills with TCL, Python or C/C++

Analytical skills

Education

PhD/BS/MS in Electrical Engineering

Tools

Digital Simulators

Industry standard ASIC tools

Job description

Job Title: Sr. IC Digital Verification Engineer

Location: Barcelona, Ottobrunn, Germany - Any, Netherlands - Any, Lisbon, Porto, Portugal - Any

Salary Range: Negotiable

Job Summary:

A Senior Digital Verification Engineer will define and lead the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions.

Essential Functions:

1. UVM and System Verilog based Digital Verification environment definition and development.
2. VIPs standardization, definition, development and documentation.
3. Define VIP’s integration into the Project’s Digital Verification environment.
4. Digital Verification Metrics definition for RTL and Gate-Level Verification.
5. Test Plan definition and development.
6. Digital Verification Automation and Scripting.
7. Regression’s infrastructure definition, development and management.
8. Close interaction with Senior Digital and Analog Designers to develop VIP models.
9. Lead the Digital Verification Team.
10. Lead and Supervise Digital Verification Tasks of multiple projects.
11. Review Digital Verification Metrics and Results of multiple projects.
12. Define and design Digital Verification Top-Level Tests.
13. Analyze and debug test results, code coverage and functional coverage.
14. Digital Verification estimation, planning and scheduling to meet tape-out.

Qualifications:

1. PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
2. 5+ years of strong experience in both RTL and Gate-Level Verification.
3. Proficient in Digital Verification Industry Languages (UVM, System Verilog) and Standards.
4. Proficient Level in DV skills and areas: Constraint random tests, SV assertions, coverage metrics, analog and digital DV modelling, DV test plans, regression analysis and reports, UVM DV Agents (Monitor, Driver, Scoreboard), etc.
5. Solid knowledge and experience working through the entire Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc.
6. Excellent Knowledge & Use of industry standard ASIC tools/flow for daily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc.
7. Excellent scripting and automation skills using TCL, Python or C/C++.
8. Leadership skills to technically guide the DV Team and mentor Jr. DV Designers.
9. Good written/verbal communication skills and strong team work/collaboration.
10. Knowledge/Experience with the following is a plus: Embedded designs and/or firmware development, Knowledge of power management industry/applications, I2C, I3C, SPI, USB, PMBUS, GitLab.