Verification Engineer I

The Preferred Supplier; Delft; On-site; EUR 60,000 - 80,000; Full time

Job summary

A leading supplier in technology solutions based in Delft seeks an experienced engineer to develop functional models for analog and mixed-signal circuits. The role involves writing verification specifications, developing test benches, and performing full chip functional verification. Candidates should have a degree in electrical engineering and experience in analog and digital circuit design, as well as scripting skills in Perl or Python. Strong communication skills are essential for effective teamwork.

Qualifications

• BA/BS Degree or higher in electrical engineering.
• Experience with analog and digital circuit design.
• Understanding of Analog schematic and experience with Cadence Virtuoso.
• Scripting languages such as Perl / Python.
• Experience with digital design languages, such as Verilog/SystemVerilog.

Responsibilities

• Develop functional models for analog and mixed-signal circuits using Verilog or similar languages.
• Write verification specifications based on required test cases.
• Develop test benches in Verilog or similar languages/environments.
• Run verification test benches and communicate results to the team.

Skills

Analog and mixed-signal circuit design

Verilog/SystemVerilog

Scripting languages (Perl/Python)

Communication skills

Education

BA/BS Degree in electrical engineering

Tools

Cadence Virtuoso

Job description

X (Nasdaq: X), a market leader in MEMS timing, offers MEMS-based silicon timing system solutions. X configurable solutions offer a rich feature set that enables customers to differentiate their products with high performance, small size, low power, and high reliability. With over 2 billion devices shipped to date, Xp>

Job Summary

Develop function models for analog and mixed-signal circuit and perform full chip functional verification.

Responsibilities

• Develop functional models for analog and mixed-signal circuits using Verilog or similar languages
• Write verification specifications based on requited test cases
• Develop test benches in Verilog or similar languages/environments to verify the top level functions of full chips
• Run verification test benches and communicate results to the team for any fixes/improvements

Qualifications & Requirements

• BA/BS Degree or higher in electrical engineering
• Experience with analog and digital circuit design
• Understanding of Analog schematic and experience with Cadence Virtuoso
• Scripting languages such as Perl / Python
• Experience with digital design languages, such as Verilog/SystemVerilog

Desired Characteristics & Attributes

• Excellent written and verbal communication skills required
• Understanding of mixed signal designs verification flow (modelsim/questasim)