Turing Chip Project- IP Verification Engineer

XPENG; Kuala Lumpur; Presencial; MYR 100.000 - 179.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Attractive salary package incl. with a

pension

Bonus potential

Descripción de la vacante

XPENG in Malaysia is seeking an experienced IP verification engineer to participate in development and verification of core IP modules, plan verification strategies, and drive coverage convergence.

You will build testbenches with SystemVerilog/UVM, develop test cases, and lead a verification team to achieve IP tape-out and delivery, supporting architecture, RTL, and prototype development. The role calls for senior to staff level experience with strong programming and debugging skills.

Formación

• Solid academic foundation in digital circuits, integrated circuits, signals and systems, linear algebra, computer architecture, and C programming.
• Familiar with digital IC design and development flows.
• Proficient in Verilog RTL coding and testbench development for simulation.
• Good understanding of AXI, CSI, MIPI, and other related protocols.
• Good understanding of image formats and image processing algorithms.
• Strong programming and debugging capabilities.
• Familiar with mainstream verification methodologies (UVM, SVA, etc.).
• Capable of independently completing full-cycle verification of a brand-new module from scratch.
• 3–10 years of experience in the verification industry (Senior: 3–5 years; Staff: 6–10 years).

Responsabilidades

• Participate in the development and verification of core IP modules.
• Plan verification strategies, develop verification plans based on product features, and decompose test points.
• Build testbenches using SystemVerilog/UVM, develop test cases, and drive coverage convergence.
• Complete IP functional, performance, and power verification; support SoC integration verification and gate-level simulation.
• Support verification activities during architecture design, RTL coding, and prototype development.
• Build and manage the verification team, leading the team to achieve successful IP tape-out and delivery (for Staff level).

Conocimientos

Digital IC verification

Verilog RTL

UVM

SystemVerilog

Testbench development

IP verification leadership

Programming debugging

Verification methodologies

Full-cycle verification

Herramientas

Verilog RTLcoding

UVM

SVA

Descripción del empleo

Responsibilities

• 1. Participate in the development and verification of core IP modules.
• 2. Plan verification strategies, develop verification plans based on product features, and decompose test points.
• 3. Build testbenches using SystemVerilog/UVM, develop test cases, and drive coverage convergence.
• 4. Complete IP functional, performance, and power verification; support SoC integration verification and gate-level simulation.
• 5. Support verification activities during architecture design, RTL coding, and prototype development.
• 6. Build and manage the verification team, leading the team to achieve successful IP tape-out and delivery (for Staff level).

Requirements

• 1. Solid academic foundation in digital circuits, integrated circuits, signals and systems, linear algebra, computer architecture, and C programming.
• 2. Familiar with digital IC design and development flows.
• 3. Proficient in Verilog RTL coding and testbench development for simulation.
• 4. Good understanding of AXI, CSI, MIPI, and other related protocols.
• 5. Good understanding of image formats and image processing algorithms.
• 6. Strong programming and debugging capabilities.
• 7. Familiar with mainstream verification methodologies (UVM, SVA, etc.).
• 8. Capable of independently completing full-cycle verification of a brand-new module from scratch.
• 9. 3–10 years of experience in the verification industry (Senior: 3–5 years; Staff: 6–10 years).

Preferred Qualifications

• 1.Experience in IP or SoC verification for vision processing, image processing, or ADAS.
• 2.Experience in FPGA or emulator development and debugging.
• 3.Familiar with formal verification tools (FPV/DPV).
• 4.Good understanding of neural network algorithms.
• 5.Familiar with CPU, GPU, and NPU architectures and instruction sets.
• 6.Experience in parallel computing and acceleration IP development.
• 7.Proven experience in leading teams and delivering complete IP projects (for Staff level).
• 8.Experience in leveraging AI to assist and accelerate verification, automating flows, and improving verification efficiency and quality.

XPENG offers:

• An interesting, unique and very varied job at XPENG
• A job with an incredibly large contact surface both internally and externally
• An attractive salary package incl. pension and with the possibility of a bonus
• To be involved in the growth of an existing EV brand in Europe

Next steps

For more information on how we process your personal data, please see: https://www.xpeng.com/policy

As part of our application process, certain positions at our company require a pre-employment screening to ensure the reliability and integrity of our employees. This screening is a standard procedure and may include components such as a Criminal Background Check from your current or previous country of residence over the past five years. Additionally, the process may involve an integrity questionnaire, verification of identification, diplomas, work experience, and consultation of the central insolvency register.

We appreciate your understanding and cooperation in this important matter, as it helps us maintain the high standards expected by our team.

Our Commitment to Diversity and Inclusion

At XPENG, we’re an equal-opportunity employer that values diversity and positively encourages applications from suitably qualified and eligible candidates regardless of race, religion, sex, national origin, gender, sexual orientation, age, marital status, disability status or other applicable legally protected characteristics.