Turing Chip Project- Senior / Staff SoC Solution and Micro-architecture Engineer Multimedia IP / System Integration

XPENG; Kuala Lumpur; On-site; MYR 120,000 - 210,000; Full time

Benefits offered by this job

An interesting, unique and very varied

Salary package incl. pension with a/b

Bonus potential

Growth in EV brand in Europe

Job summary

XPENG is seeking a SoC Engineer with strong ASIC/SoC front-end experience to work on solution design, micro-architecture definition, IP ownership and subsystem integration for multimedia and perception related subsystems.

The role covers camera, ISP, display processor, video codec, DSP/multimedia accelerators and related interfaces. You will collaborate with RTL, verification, backend, software and system teams to deliver IP and subsystem integration and optimize performance.

Qualifications

• Bachelor’s degree or above in Electrical Engineering, Microelectronics, Computer Engineering, Automation, or related fields.
• 3+ years of ASIC/SoC front-end design, IP design, subsystem design, or SoC integration experience.
• Solid understanding of SoC/IP design methodology including spec, micro-architecture, RTL support, verification, and tapeout.
• Familiar with Verilog/SystemVerilog; RTL understanding preferred.
• Familiar with AXI/AB/APB, NoC/fabric, DMA, interrupts, clock/reset, memory subsystem, debug and security.
• Experience in IP/subsystem integration including interface adaptation and clock/power domains.
• Experience in high-throughput multimedia datapath design with pipelines, buffers, QoS, latency, and trade-offs.
• Hands-on project experience in camera/ISP, display, video codec, DSP/accelerator, MIPI/DP, or SoC integration.
• Ability to read and write English technical documents.
• Strong cross-functional communication and issue-closure capability.

Responsibilities

• Participate in solution definition, module partitioning, and micro-architecture design for multimedia and perception‑related SoC subsystems.
• Own or contribute to technical solution design for camera, ISP, display, video, DSP/accelerator, multimedia interface, or SoC integration IPs and subsystems.
• Define key IP/subsystem micro-architecture, including datapath, control path, DMA, buffers, registers, interrupts, debugging, and power management.
• Participate in internal or third‑party IP evaluation, selection, parameter configuration, wrapper design, and interface adaptation.
• Own or support integration of IPs with SoC fabric, memory, CPU/DSP/NPU/GPU, firmware/software, and debug/trace infrastructure.
• Analyze and optimize multimedia performance, bandwidth, latency, QoS, and power trade-offs.
• Develop and maintain architecture proposals, micro-architecture specs, integration guidelines, and interface specs.
• Work with RTL, verification, backend, software, driver, algorithm, system, and project teams on design reviews and silicon bring-up.

Skills

ASIC front-end

SoC integration

IP design

RTL/Verilog understanding

Interface protocols

English technical docs

Cross-functional communication

Education

Bachelor's degree or above

Tools

Verilog/SystemVerilog

AXI/NoC interfaces

DMA & memory subsystem

MIPI/DP interfaces

Job description

We are looking for a SoC Engineer with strong ASIC / SoC front-end experience to work on solution design, micro-architecture definition, IP integration, and system integration for multimedia and perception-related SoC subsystems.

The role may cover camera, ISP, display processor, video codec, DSP / multimedia accelerators, MIPI / DisplayPort interfaces, and SoC subsystem integration. Candidates are not expected to cover all areas, but should have hands-on project experience in one or more relevant IP, subsystem, or system integration domains.

This role focuses on solution design, micro-architecture, IP ownership, and subsystem integration.

Key Responsibilities

1.Participate in solution definition, module partitioning, and micro-architecture design for multimedia and perception-related SoC subsystems based on product, system, and SoC architecture requirements.

2.Own or contribute to technical solution design for camera, ISP, display, video, DSP / accelerator, multimedia interface, or SoC integration related IPs and subsystems.

3.Define key IP or subsystem micro-architecture, including datapath, control path, DMA, buffers, register models, interrupts, debug, error handling, clock/reset, and power management.

4.Participate in internal or third-party IP evaluation, selection, parameter configuration, wrapper / adaptor design, interface adaptation, and SoC integration.

5.Own or support integration of IPs and subsystems with SoC fabric, memory subsystem, CPU / DSP / NPU / GPU, firmware / software, clock/reset, power domains, security / firewall, and debug / trace infrastructure.

6.Analyze and optimize multimedia performance, bandwidth, latency, and power, including resolution, frame rate, multi-stream scenarios, memory bandwidth, QoS, buffer sizing, pipeline depth, clock frequency, and area / power / performance trade-offs.

7.Develop and maintain key design documents, including architecture proposals, micro-architecture specifications, IP integration specifications, register specifications, interface specifications, performance analysis, and integration guidelines.

8.Work with RTL, verification, backend, software, driver, algorithm, system, and project teams on design review, verification planning, integration closure, tapeout support, and silicon bring-up.

Support complex issue analysis and closure across interface protocols, data flow, bandwidth bottlenecks, clock/reset, CDC/RDC, low power, timing, DFT, software configuration, and post-silicon debug.

Requirements

1.Bachelor’s degree or above in Electrical Engineering, Microelectronics, Computer Engineering, Communication Engineering, Automation, or related fields.

2.3+ years of ASIC / SoC front-end design, IP design, subsystem design, or SoC integration experience. Experience requirements may be adjusted for exceptional candidates.

3.Solid understanding of SoC / IP design methodology, including specification, solution proposal, micro-architecture, RTL implementation support, verification support, integration support, and tapeout support.

4.Familiarity with Verilog / SystemVerilog and ability to understand and review RTL design quality. RTL coding experience is preferred.

5.Familiarity with AXI / AHB / APB, NoC / fabric, DMA, interrupts, clock/reset, power domains, memory subsystem, debug, security, and register interfaces.

6.Experience in IP or subsystem integration, including interface adaptation, parameter configuration, register mapping, clock/reset, power domains, bandwidth / QoS, CDC/RDC, and integration closure.

7.Experience in high-throughput multimedia datapath design or analysis, with understanding of pipelines, buffers, back-pressure, bandwidth, latency, QoS, and area / power / performance trade-offs.

8.Hands-on project experience in at least one of the following areas: camera / ISP, display, video codec, DSP / accelerator, MIPI, DP/eDP, or SoC integration.

9.Ability to read and write English technical documents.

10.Strong cross-functional communication and issue-closure capability.

Preferred Qualifications

1.Experience as a subsystem owner, IP owner, micro-architecture owner, technical lead, or SoC integration owner.

2.Experience with automotive SoC, intelligent cockpit, ADAS, robotics, AIoT, or high-performance multimedia SoCs.

3.Familiarity with multimedia and vision business scenarios and applications, such as camera / perception pipelines, intelligent cockpit display and video use cases, ADAS / robotics sensor processing, multi-camera streaming, low-latency preview, recording, playback, and user‑experience constraints.

4.Familiarity with Linux drivers, V4L2, DRM/KMS, camera / display / video driver flows, or firmware bring‑up.

5.Experience with FPGA, emulation, silicon bring‑up, customer issue debug, or production tapeout.

6.Familiarity with ISO 26262, ASIL, AEC-Q100, functional safety, or automotive quality flow.

7.Experience with third‑party IP integration, IP vendor collaboration, IP delivery review, or IP quality assessment.

XPENG offers:

• An interesting, unique and very varied job at XPENG
• A job with an incredibly large contact surface both internally and externally
• An attractive salary package incl. pension and with the possibility of a bonus
• To be involved in the growth of an existing EV brand in Europe

As part of our application process, certain positions at our company require a pre‑employment screening to ensure the reliability and integrity of our employees. This screening is a standard procedure and may include components such as a Criminal Background Check from your current or previous country of residence over the past five years. Additionally, the process may involve an integrity questionnaire, verification of identification, diplomas, work experience, and consultation of the central insolvency register.

We appreciate your understanding and cooperation in this important matter, as it helps us maintain the high standards expected by our team.

Our Commitment to Diversity and Inclusion:

At XPENG, we’re an equal‑opportunity employer that values diversity and positively encourages applications from suitably qualified and eligible candidates regardless of race, religion, sex, national origin, gender, sexual orientation, age, marital status, disability status or other applicable legally protected characteristics.