Testchip Design Engineer

Intel Corporation; Seberang Perai; Hybrid; MYR 180,000 - 300,000; Full time

Job summary

Intel Corporation in Malaysia (Penang) is seeking a Senior Engineer to lead end-to-end testchip design and execution for advanced process nodes. You will own schedules, guide design rule interpretation, and drive layout and test-structure delivery with cross-functional teams.

You will apply automation and AI techniques to accelerate runs, mentor engineers, and coordinate across sites to meet specifications and timelines. Hybrid work model offered in Malaysia.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 8+ years of hands-on experience in layout design, test structure development, and flow methodology.
• Strong ability to interpret design rules and runsets for advanced nodes.
• Full testchip design flow experience from spec to Tape-In delivery.
• Proven scripting skills (Python/Tcl/Perl) with automation and AI leverage.

Responsibilities

• Lead end-to-end testchip design and execution for advanced process nodes.
• Own overall schedule across multiple component blocks to ensure quality and delivery through Tape-In.
• Define comprehensive test structure requirements and collaborate with yield/process teams.
• Oversee full-flow layout execution from setup to DRC-clean sign-off with quality gates.
• Deliver Testrow Integration including generation, fill, checks, and signal verification on schedule.
• Define and deploy automation and AI strategies for repetitive tasks and reporting.
• Mentor junior and mid-level engineers and drive cross-site collaboration.

Skills

Testchip design

Layout execution

Runset interpretation

Automation scripting

AI for layout

Team leadership

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree preferred

Tools

Python

Tcl

Perl

Job description

Job Details:

Job Description:

We are seeking a highly skilled and motivated Senior Engineer to lead end-to-end testchip design and execution for advanced process technology nodes. This is a hands-on technical leader role that combines deep expertise in design rule validation, test structure design, and layout execution with strong cross-functional collaboration and program management capabilities.

Drive testchip execution end-to-end by owning the overall schedule across multiple component blocks, serving as the primary accountability owner for quality and delivery through Tape-In while providing hands-on technical guidance to the team.

Apply deep design rule and runset expertise to interpret design rules on advance design process, defining comprehensive test structure requirements and collaborating with yield and process teams to drive iterative design loops to full specification compliance.

Own the full-flow layout execution across all cell heights and layers, from environment setup and test structure layout design through DRC-clean sign-off, enforcing clear quality gates at each stage.

Deliver integration and Tape-In on schedule by driving Testrow Integration covering generation, fill, design checks, and signal plot verification, ensuring all content check-in and health checks are completed before final Tape-In handoff.

Define and deploy an automation and AI strategy targeting repetitive execution tasks - DRC runs, layout automation, test structure validation, and reporting - leveraging AI tools and building agents where applicable to accelerate execution throughput and reduce manual intervention.

Lead cross-site collaboration and communication as the key technical interface between design, yield, process, and integration teams across distributed sites, aligning on specifications, schedules, and priorities while communicating proactively in all directions.

Mentor and grow the team by coaching junior and mid-level engineers on design rule interpretation, test structure methodology, and execution best practices, setting clear expectations and actively raising the technical bar across the group.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field required; Master's degree preferred
• 8+ years of hands-on experience in layout design, test structure development, and flow methodology, with a strong track record of driving corecells and DUTs to DRC-clean sign-off on advanced process nodes.
• Deep knowledge or advance design rules with ability to interpret runset into effective test structure strategies.
• Solid understanding of the full testchip design flow from specification and layout through integration and Tape-In delivery.
• Proven scripting skills (Python, Tcl, Perl, or equivalent) with experience deploying automation and leveraging AI tools or agents for layout automation and test structure validation.
• 5+ years of proven experience leading and managing teams with a strong record of delivery, including project progress tracking and reporting across cross-site stakeholders.
• Strong written and verbal skills with ability to present complex technical content clearly to technical and management audiences.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*

ADDITIONAL INFORMATION:

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.