Testchip Design Engineer

Intel Corporation; Kuala Lumpur; Hybrid; MYR 180,000 - 240,000; Full time

Job summary

Intel Corporation in Penang, Malaysia seeks a Testchip Design Engineer to lead end-to-end testchip design and execution for advanced process nodes. This hands-on technical leader role combines design rule validation, test structure development, and layout execution with program management across multiple blocks.

You will drive Tape-In delivery, define automation and AI strategies for repetitive tasks, mentor engineers, and collaborate across design, yield, and process teams to ensure on-time,

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 8+ years hands-on experience in layout design, test structure development, and flow methodology.
• Deep knowledge of design rules and ability to interpret runset into test structures.
• Proficient in scripting and automation for layout and test structure validation.

Responsibilities

• Lead end-to-end testchip design and execution for advanced process nodes.
• Own schedule across multiple blocks and ensure timely Tape-In delivery with quality gates.
• Drive automation and AI strategies to reduce manual tasks and accelerate throughput.

Skills

Testchip design leadership

Design rule validation

Runset interpretation

Automation strategy

Scripting

Team mentoring

Education

Bachelor's degree in Electrical Engineering

Bachelor's degree in Computer Engineering

Master's degree (preferred)

Tools

Python

Tcl

Perl

Job description

## Testchip Design EngineerApply: Malaysia, Penang: Full time: Posted Today: JR0288010# **Job Details:**## Job Description:We are seeking a highly skilled and motivated Senior Engineer to lead end-to-end testchip design and execution for advanced process technology nodes. This is a hands-on technical leader role that combines deep expertise in design rule validation, test structure design, and layout execution with strong cross-functional collaboration and program management capabilities. * **Drive testchip execution end-to-end** by owning the overall schedule across multiple component blocks, serving as the primary accountability owner for quality and delivery through Tape-In while providing hands-on technical guidance to the team. * **Apply deep design rule and runset expertise** to interpret design rules on advance design process, defining comprehensive test structure requirements and collaborating with yield and process teams to drive iterative design loops to full specification compliance. * **Own the full-flow layout execution** across all cell heights and layers, from environment setup and test structure layout design through DRC-clean sign-off, enforcing clear quality gates at each stage. * **Deliver integration and Tape-In on schedule** by driving Testrow Integration covering generation, fill, design checks, and signal plot verification, ensuring all content check-in and health checks are completed before final Tape-In handoff. * **Define and deploy an automation and AI strategy** targeting repetitive execution tasks — DRC runs, layout automation, test structure validation, and reporting — leveraging AI tools and building agents where applicable to accelerate execution throughput and reduce manual intervention. * **Lead cross-site collaboration and communication** as the key technical interface between design, yield, process, and integration teams across distributed sites, aligning on specifications, schedules, and priorities while communicating proactively in all directions. * **Mentor and grow the team** by coaching junior and mid-level engineers on design rule interpretation, test structure methodology, and execution best practices, setting clear expectations and actively raising the technical bar across the group. ## **Qualifications:**You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. * Bachelor's degree in Electrical Engineering, Computer Engineering, or related field required; Master's degree preferred * 8+ years of hands-on experience in layout design, test structure development, and flow methodology, with a strong track record of driving corecells and DUTs to DRC-clean sign-off on advanced process nodes. * Deep knowledge or advance design rules with ability to interpret runset into effective test structure strategies. * Solid understanding of the full testchip design flow from specification and layout through integration and Tape-In delivery. * Proven scripting skills (Python, Tcl, Perl, or equivalent) with experience deploying automation and leveraging AI tools or agents for layout automation and test structure validation. * 5+ years of proven experience leading and managing teams with a strong record of delivery, including project progress tracking and reporting across cross-site stakeholders. * Strong written and verbal skills with ability to present complex technical content clearly to technical and management audiences.## Job Type:Experienced Hire## Shift:Shift 1 (Malaysia)## Primary Location:Malaysia, Penang## Additional Locations:## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. \\* Job posting details (such as work model, location or time type) are subject to change.