Sr Application Engineer

Cadence Design Systems; Kuala Lumpur; On-site; MYR 120,000 - 180,000; Full time

Job summary

Cadence Design Systems in Malaysia seeks a Sr Application Engineer to support Cadence digital implementation, physical design, and static verification solutions locally. You will lead hands-on physical design tasks, collaborate with RTL teams, and help customers achieve optimal PPA on advanced nodes.

The role involves floorplanning, power grid design, place & route, CTS, timing closure, and stakeholder engagement with Cadence R&D; requires strong English communication and a proactive,

Qualifications

• BS/MS in EE/CS with 2+ years of hands-on experience in physical design and verification.
• Experience with 7nm and below technologies.
• Knowledge of ASIC design flow, hierarchical physical design methodologies.
• Strong knowledge of Low Power Design.
• Ability to work independently and in a team; excellent English communication.

Responsibilities

• Perform physical design implementation: floorplanning, power grid design, place and route, clock tree synthesis, timing closure.
• Tackle diverse designs, including low power and high-speed variants at latest nodes.
• Participate in or lead next-generation physical design methodology and flow development.
• Collaborate with RTL design teams to ensure successful tapeouts.

Skills

Physical design

Verification

ASIC design flow

Low power design

Timing closure

7nm technology

Education

BS/MS in EE/CS

Job description

## Sr Application EngineerApply: PENANG 02: Full time: Posted Today: R56729## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**Sr Application Engineer – Digital Implementation & Physical DesignLocation: MalaysiaJob OverviewWe are seeking a Sr Application Engineer to support and drive the adoption of Cadence’s digital implementation, physical design, and static verification solutions across key customers in the region.In this role, you will combine deep hands-on physical design expertise with technical leadership and customer engagement, helping customers achieve optimal performance, power, and area (PPA) on advanced technology nodes. You will work closely with customer design teams, Cadence R&D, Product Engineering influencing methodologies and ensuring successful project execution and tool adoption.• The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure• The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high-speed designs at the latest technology nodes.• The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.• The candidate will work closely with RTL design team to ensure successful tapeouts.Requirement:• BS/MS in EE/CS with 2+ years of hands-on experience in physical design and verification with prior working experience in 7nm and below technologies.• Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues.• Solid knowledge on Low Power Design• Able to assume responsibility for a variety of technical tasks and to work independently• Self-motivated, able to work as a team player, and good English communication skills