Sr Application Engineer

Cadence Design Systems; George Town; On-site; MYR 120,000 - 180,000; Full time

Job summary

Cadence Design Systems is seeking a Senior Application Engineer to support and drive adoption of digital implementation, physical design and static verification solutions across the region in Malaysia. You will combine hands-on physical design with technical leadership and customer engagement to optimize performance, power and area, working closely with customer design teams and Cadence R&D.

You will participate in or lead next generation physical design methodology and flow development and

Qualifications

• Hands-on experience in physical design and verification
• Experience with 7nm and below technologies
• Solid knowledge on Low Power Design

Responsibilities

• Perform physical design implementation: floor planning, power grid design, place and route, clock tree synthesis, timing closure
• Work on challenging designs including low power and high-speed at latest nodes
• Participate in or lead next generation physical design, methodology and flow development
• Collaborate with RTL design team to ensure successful tapeouts

Skills

Physical design

ASIC design flow

Low power design

English communication

Independent / self-motivated

Education

BS/MS in EE/CS

Job description

Sr Application Engineer – Digital Implementation & Physical Design

Location: Malaysia

Job Overview

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We are seeking a Sr Application Engineer to support and drive the adoption of Cadence’s digital implementation, physical design, and static verification solutions across key customers in the region. In this role, you will combine deep hands-on physical design expertise with technical leadership and customer engagement, helping customers achieve optimal performance, power, and area (PPA) on advanced technology nodes. You will work closely with customer design teams, Cadence R&D, Product Engineering influencing methodologies and ensuring successful project execution and tool adoption.

• The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure
• The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high-speed designs at the latest technology nodes
• The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development
• The candidate will work closely with RTL design team to ensure successful tapeouts

Requirement:

• BS/MS in EE/CS with 2+ years of hands-on experience in physical design and verification with prior working experience in 7nm and below technologies
• Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues
• Solid knowledge on Low Power Design
• Able to assume responsibility for a variety of technical tasks and to work independently
• Self-motivated, able to work as a team player, and good English communication skills

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.