Senior DFT Engineer: SoC Test Architecture & ATPG

Eternity Recruitment; Bayan Lepas; On-site; MYR 120,000 - 180,000; Full time

Job summary

Eternity Recruitment’s client seeks an experienced DFT Engineer to design, implement, and optimize DFT solutions for ASIC/SoC designs. You will drive ATPG, scan insertion, and fault simulation while improving test coverage across silicon stages.

Key responsibilities include DFT architecture, scanning, netlist/timing simulations, and working with Cadence Modus, Tessent/TestKompress, and TetraMAX/TestMAX. Strong scripting (TCL/Python/Perl) and cross-functional collaboration are essential.

Qualifications

• Bachelor's or Master's Degree in Electrical & Electronic Engineering, Microelectronics, Semiconductor Engineering or a related field
• At least 5-year experience and above in related field
• Relevant experience in DFT / SoC design and implementation
• Strong knowledge of DFT concepts, including Scan Architecture, ATPG, Fault Models and Test Compression
• Hands‑on experience with ATPG, scan insertion and fault simulation
• Experience in stuck‑at fault and at‑speed pattern generation
• Experience in ATPG coverage analysis, timing simulations, debugging and improvement
• Experience with industry‑standard DFT tools such as Cadence Modus, Siemens Tessent / TestKompress, Synopsys TetraMAX / TestMAX
• Experience with TCL, Python or Perl scripting
• Strong analytical and problem‑solving skills with the ability to work effectively in a cross‑functional team

Responsibilities

• Define and implement DFT architecture for SoCs and sub-systems
• Insert and verify Scan, MBIST, LBIST and Boundary Scan structures
• Perform scan insertion, ATPG and fault simulation
• Generate stuck-at-fault and at-speed test patterns
• Perform ATPG netlist and timing simulations
• Analyse ATPG coverage and identify opportunities to improve test coverage
• Work with various fault models including stuck-at, transition and path-delay faults
• Debug and resolve DFT and ATPG issues during simulation and silicon stages
• Support DFT coverage analysis, debug and optimization
• Perform MBIST insertion, pattern generation and netlist/timing simulations where required

Skills

DFT

ATPG

Scan Architecture

MBIST

LBIST

Boundary Scan

Pattern Generation

Fault Simulation

Test Coverage

Scripting: TCL/Python/Perl

Cadence Modus

Tessent/TestKompress

Synopsys TetraMAX/TestMAX

VLSI DFT Tools

Education

Bachelors or Masters in Electrical & Electronic Engineering / Microelectronics

Tools

Cadence Modus

Siemens Tessent / TestKompress

Synopsys TetraMAX / TestMAX

Job description

Eternity Recruitment’s client seeks an experienced DFT Engineer to design, implement, and optimize DFT solutions for ASIC/SoC designs. You will drive ATPG, scan insertion, and fault simulation while improving test coverage across silicon stages.

Key responsibilities include DFT architecture, scanning, netlist/timing simulations, and working with Cadence Modus, Tessent/TestKompress, and TetraMAX/TestMAX. Strong scripting (TCL/Python/Perl) and cross-functional collaboration are essential.