SoC RTL Design Engineer — Flexible Hours

CHING ELECTRIC & ENGINEERING SDN. BHD.; Penang; On-site; MYR 120,000 - 180,000; Full time

Benefits offered by this job

Flexible hours

Job summary

CHING ELECTRIC & ENGINEERING SDN. BHD. in Penang, Malaysia, is hiring a Full time Design Engineer to join our SoC team. We welcome junior to senior engineers to craft RTL code and integrate RTL blocks for cutting-edge devices.

Responsibilities include Verilog/VHDL design, STA timing checks, SDC creation, and collaboration on testing and production-ready releases. Flexible hours available and a strong foundation in digital design is essential.

Qualifications

• Bachelor’s or Master’s in Electrical/Computer Engineering
• Minimum 2 years experience in digital circuit design
• Proficient in Verilog/VHDL with exposure to verification tools
• Knowledge of STA and timing analysis
• Scripting know-how (Python, Perl, etc.)
• Analytical problem-solver and team player

Responsibilities

• Craft high-quality RTL code (Verilog/VHDL) powering SoCs.
• Own RTL integration: coding, checkers, SDC, timing collaterals, routing design.
• Run STA and ensure designs meet performance targets.
• Create SDCs, linting & CDC checks.
• Integrate circuits into larger systems.
• Collaborate on testing and release for production-ready designs.

Skills

RTL design

Verilog/VHDL

STA analysis

SDCs

Linting

CDC checks

Python

Problem solving

Team player

Independent work

Education

Bachelors/Masters in ECE

Tools

Verification tools

Job description

CHING ELECTRIC & ENGINEERING SDN. BHD. in Penang, Malaysia, is hiring a Full time Design Engineer to join our SoC team. We welcome junior to senior engineers to craft RTL code and integrate RTL blocks for cutting-edge devices.

Responsibilities include Verilog/VHDL design, STA timing checks, SDC creation, and collaboration on testing and production-ready releases. Flexible hours available and a strong foundation in digital design is essential.