SOC DFX RTL Design Engineer - Frontend & Debug

AMD; Seberang Perai; On-site; MYR 90,000 - 150,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD in Penang, Malaysia, is seeking engineers for the Radeon Technologies Group focusing on DFX design, verification, and integration across front-end design teams. The role involves enabling JTAG/Scan features, boundary scan, and debug capabilities in next-generation processors.

The ideal candidate has hands-on experience with Verilog/SystemVerilog, RTL simulations, and multiple scripting languages. You will collaborate with architecture, IP design, and product engineers across sites to ensure

Qualifications

• Bachelors or Masters degree in computer engineering or electrical engineering.
• Experience with DFX/DFX techniques and related standards.
• Knowledge of Verilog RTL and gate-level simulations.
• Proficiency with EDA tools and wave debugging.
• Experience with scripting (Python, Perl, TCL).
• Team player with strong communication across time zones.

Responsibilities

• DFX design planning and implementation of DFX features (JTAG, Scan, Boundary Scan, Debug).
• Collaborate with CAD/IP teams on requirements and power scenarios.
• Work with DFX Verification team for quality.
• Participate in DFX initiatives and process development.
• Provide technical support to cross-functional teams.
• Collaborate with team members.

Skills

Verilog

SystemVerilog

C/C++

Python

Perl scripting

TCL scripting

VCS

DFX knowledge

RTL debugging

Scripting languages

Education

Bachelors or Masters in computer engineering or electrical engineering

Tools

Mentor TestKompress

Synopsys Tetramax/DFTMax

VCS simulation tool

Job description

AMD in Penang, Malaysia, is seeking engineers for the Radeon Technologies Group focusing on DFX design, verification, and integration across front-end design teams. The role involves enabling JTAG/Scan features, boundary scan, and debug capabilities in next-generation processors.

The ideal candidate has hands-on experience with Verilog/SystemVerilog, RTL simulations, and multiple scripting languages. You will collaborate with architecture, IP design, and product engineers across sites to ensure