Senior USB IP Verification Architect

Jobtailor; Penang; On-site; MYR 180,000 - 300,000; Full time

Job summary

Jobtailor in Malaysia is seeking an experienced RTL design verification engineer to develop functional verification plans and test benches covering microarchitectural specs. The role requires collaboration with architects and RTL/physical teams, using SystemVerilog and UVM/OVM for thorough pre-silicon validation.

You will execute verification strategies, debug failing tests, and improve verification infrastructure while documenting plans and leading reviews.

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or equivalent.
• 6–8 years of RTL design verification experience.
• Expertise in SystemVerilog and UVM/OVM methodologies.
• Experience with pre-silicon verification tools such as VCS/Synopsys and scripting languages like Python/Perl/Shell.
• Understanding of high-speed IO IPs such as USB, PCI Express, or AMBA protocols.

Responsibilities

• Develop functional verification plans and test benches to cover microarchitecture specifications.
• Execute verification strategies through system simulation models to analyze power, timing, and functionality while identifying and resolving bugs.
• Implement corrective measures to address failing tests and debug issues in the presilicon environment.
• Collaborate with architects, RTL developers, and physical design teams to validate complex architectural and microarchitectural features.
• Maintain and improve functional verification infrastructure and methodologies to support ongoing innovation.
• Document test plans and lead technical reviews with design and architecture teams to ensure alignment with project goals.
• Drive improvements in test coverage, efficiency, and execution time through innovative problem‑solving and validation techniques.

Skills

RTL verification

SystemVerilog

UVM/OVM

test plan design

testbench development

cross-functional collaboration

Education

Bachelor's degree in EE/EC/CS

Master's/PhD preferred

Tools

VCS/Synopsys

Python

Perl

Shell

BFMs

Job description

Jobtailor in Malaysia is seeking an experienced RTL design verification engineer to develop functional verification plans and test benches covering microarchitectural specs. The role requires collaboration with architects and RTL/physical teams, using SystemVerilog and UVM/OVM for thorough pre-silicon validation.

You will execute verification strategies, debug failing tests, and improve verification infrastructure while documenting plans and leading reviews.