Senior Digital Verification Engineer: Drive UVM/RTL Testing

Career Wise; Penang; On-site; MYR 111,600 - 167,400; Full time

Job summary

A leading recruitment firm in Malaysia is looking for a Sr. Digital Verification Engineer. The role involves collaborating with architects and engineers to verify new features, building comprehensive test plans, and debugging test failures. Candidates should have 5-15 years of experience in digital IP verification using SV/UVM, and proficiency in Bahasa Melayu, English, and Mandarin is essential for communication with clients in China. This position requires strong skills in ASIC verification and debugging firmware.

Qualifications

• Min 5 - 15 years of experience in digital IP verification with SV/UVM formal verification or new methodologies.
• Good understanding of UVM concepts and System Verilog language.
• Proficiency in Bahasa Melayu, English, and Mandarin for communication with customers.

Responsibilities

• Collaborate with architects and engineers to verify new features.
• Build test plan documentation for various interactions.
• Estimate time to write tests and required changes.
• Build directed and random verification tests.
• Debug test failures and resolve design defects.
• Review coverage metrics and modify tests as needed.

Skills

IP/SoC level ASIC verification

Debugging firmware and RTL code

UVM testbenches

Verilog

System Verilog

C

C++

Scripting languages (Perl, Ruby, Shell)

Leadership or mentorship

Job description

A leading recruitment firm in Malaysia is looking for a Sr. Digital Verification Engineer. The role involves collaborating with architects and engineers to verify new features, building comprehensive test plans, and debugging test failures. Candidates should have 5-15 years of experience in digital IP verification using SV/UVM, and proficiency in Bahasa Melayu, English, and Mandarin is essential for communication with clients in China. This position requires strong skills in ASIC verification and debugging firmware.