Senior Staff Design Engineer

Lattice Semiconductor; Penang; On-site; MYR 180,000 - 300,000; Full time

Job summary

Lattice Semiconductor in Malaysia is seeking a Senior Staff Engineer to lead development, integration, and productization of high-performance interface solutions for next-generation FPGA products. You will own subsystems across PCIe, USB, MIPI, SerDes, and related PHY technologies, collaborating with hardware, software, and design teams.

The role demands a deep RTL background, strong architectural judgment, and the ability to drive cross-functional delivery from pre-silicon to silicon bring-up,

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• 15+ years of experience in ASIC, SoC, or FPGA design and product-development.
• Strong RTL design and subsystem integration experience, including clock/reset architecture, configuration interfaces, timing, and CDC/RDC considerations.
• Deep expertise in at least one high-speed interface area such as PCIe, USB, MIPI, SerDes, or related PHY/controller technology.
• Demonstrated ability to understand an interface as a complete subsystem and drive dependencies beyond the RTL block.
• Experience applying AI-assisted tools and workflows to accelerate engineering productivity, technical investigation, data analysis, and documentation.
• Experience working with DFT and DFD methodologies, including scan, ATPG, debug observability, silicon bring-up, or production-test considerations.
• Experience leading complex cross-functional debug and driving issues from initial investigation through verified closure.
• Experience with pre-silicon verification, silicon bring-up, laboratory debug, interoperability, or customer issue resolution.
• Strong technical communication, stakeholder alignment, and independent decision-making skills.

Responsibilities

• Lead architecture and micro-architecture, RTL development, integration, verification, and productization of PCIe, USB, MIPI, SerDes, and related interface subsystems.
• Own subsystem requirements and dependencies across digital logic, PHY/PMA, soft IP, firmware, FPGA software tools, package, platform, and validation.
• Drive structured root-cause analysis for complex pre-silicon, post-silicon, software-interaction, interoperability, and customer-reported issues.
• Work with software and firmware teams to define configuration, feature enablement, diagnostic, and user-flow requirements.
• Drive technical engagement with third-party IP suppliers and technology partners for digital, PHY, and mixed-signal IP. Define requirements, evaluate deliverables, resolve integration and verification issues, and drive technical closure through product development and silicon bring-up.
• Identify technical risks and dependencies, support milestone and release-readiness reviews, and communicate clear recommendations to stakeholders.
• Mentor engineers and improve design, debug, review, and release methodologies across the team.

Skills

RTL design

Subsystem integration

PCIe/USB/MIPI/SerDes

DFT/DFD methodologies

silicon bring-up

AI-assisted tools

technical communication

cross-functional leadership

verification

Education

Bachelor’s or Master’s degree in Electrical/Electronics/Computer Engineering

Tools

DFT tools

EDA tools

Job description

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a "team first" organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description:

Join the winning team! Lattice is looking for a motivated and experienced Senior Staff Engineer to lead the development, integration, and productization of high-performance interface solutions, including PCI Express (PCIe), USB, MIPI, SerDes, and related PHY technologies for next-generation FPGA products.

The successful candidate will bring a subsystem ownership mindset, with strong RTL expertise and the ability to drive technical decisions across protocol architecture, PHY and analog behavior, soft IP, software and firmware enablement, package and platform integration, validation, interoperability, and customer deployment. The role works closely with hardware, analog and mixed-signal, software, validation, applications, product engineering, and external IP partners.

Key Responsibilities:

• Lead architecture and micro-architecture, RTL development, integration, verification, and productization of PCIe, USB, MIPI, SerDes, and related interface subsystems.
• Own subsystem requirements and dependencies across digital logic, PHY/PMA, soft IP, firmware, FPGA software tools, package, platform, and validation.
• Drive structured root-cause analysis for complex pre-silicon, post-silicon, software-interaction, interoperability, and customer-reported issues.
• Work with software and firmware teams to define configuration, feature enablement, diagnostic, and user-flow requirements.
• Drive technical engagement with third-party IP suppliers and technology partners for digital, PHY, and mixed-signal IP. Define requirements, evaluate deliverables, resolve integration and verification issues, and drive technical closure through product development and silicon bring-up.
• Identify technical risks and dependencies, support milestone and release-readiness reviews, and communicate clear recommendations to stakeholders.
• Mentor engineers and improve design, debug, review, and release methodologies across the team.

Required Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• 15+ years of experience in ASIC, SoC, or FPGA design and product-development.
• Strong RTL design and subsystem integration experience, including clock/reset architecture, configuration interfaces, timing, and CDC/RDC considerations.
• Deep expertise in at least one high-speed interface area such as PCIe, USB, MIPI, SerDes, or related PHY/controller technology.
• Demonstrated ability to understand an interface as a complete subsystem and drive dependencies beyond the RTL block.
• Experience applying AI-assisted tools and workflows to accelerate engineering productivity, technical investigation, data analysis, and documentation.
• Experience working with DFT and DFD methodologies, including scan, ATPG, debug observability, silicon bring-up, or production-test considerations.
• Experience leading complex cross-functional debug and driving issues from initial investigation through verified closure.
• Experience with pre-silicon verification, silicon bring-up, laboratory debug, interoperability, or customer issue resolution.
• Strong technical communication, stakeholder alignment, and independent decision-making skills.

Preferred Qualifications:

• Experience with more than one interface family, including connectivity or video protocols such as PCIe, USB, MIPI CSI-2/DSI, D-PHY/C-PHY, or SerDes.
• Understanding of PHY and mixed-signal behavior associated with high-speed interface IP, including clocking, calibration, termination, equalization, jitter, reset sequencing, power management, initialization, and bring-up. Direct analog circuit design experience is not required.
• Experience working with third-party suppliers of digital controller, PHY, or mixed-signal IP to define requirements, assess deliverables, and resolve architecture, integration, verification, and silicon issues.
• Familiarity or experience in Physical Design e.g.: Synthesis, LEC or Timing Closure.
• Experience in design quality checks methodology e.g.: Lint, CDC, RDC, Fishtail or UPF flow.
• Knowledge of firmware, device configuration, APIs, scripts, drivers, or FPGA software-tool enablement.
• Exposure to package, board, platform, signal-integrity, compliance, and interoperability considerations for high-speed interfaces.
• Experience influencing architecture or methodology and mentoring engineers across organizational boundaries.

#LI-DNP

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Malaysia

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.