Senior Staff Engineer: Package Tech & Risk Integration

Infineon Technologies

Malacca City

On-site

MYR 90,000 - 130,000

Full time

14 days+

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Job summary

Infineon Technologies seeks a seasoned engineer to lead DFMEA processes and risk analyses within the package technology domain. You will collaborate across FE/BE interfaces, integrate BOM/process data, and guide pre-development for next-gen chip tech.

The role rewards strong communication and problem-solving skills, with emphasis on reliability and cross-functional teamwork in a semiconductor environment.

Qualifications

  • Bachelor’s Degree in Engineering with extensive IC/semiconductor experience in SMT, packaging, assembly and test.
  • Strong communication, collaboration and problem-solving abilities.
  • Knowledge of FE/BE interaction and BE/BE interfaces.
  • Familiar with DFMEA/PFMEA and 8D/T6s methodologies.
  • Experience with internal package analysis and first-level reliability.

Responsibilities

  • PBC and TPC assessment.
  • Driver of Package Technology DFMEA Process of Record.
  • Owner of Risk Interaction assessment and mitigation work packages.
  • Integration of unit processes (BOM and Process) in package platform -Risk assessment, study interaction with other processes, process flow.
  • Working partner for FE in FE/BE interaction and integration topics.
  • Support Pre development for new Chip technology.

Skills

Engineering degree
Semiconductor experience
SMT knowledge
Packaging
Assembly and Test
Communication skills
DFMEA/PFMEA
8D/T6s
FE/BE interaction
Package analysis
Reliability basics

Education

Bachelor’s Degree in Engineering

Job description

Infineon Technologies seeks a seasoned engineer to lead DFMEA processes and risk analyses within the package technology domain. You will collaborate across FE/BE interfaces, integrate BOM/process data, and guide pre-development for next-gen chip tech.

The role rewards strong communication and problem-solving skills, with emphasis on reliability and cross-functional teamwork in a semiconductor environment.

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