DFT Architect

Altera; George Town; On-site; MYR 300,000 - 460,000; Full time

Job summary

Altera is seeking a DFT Architect to define, drive, and govern next‑generation DFT architecture across FPGA, SoC, and multi‑die silicon platforms. You will own the end‑to‑end DFT strategy and partner with architecture, RTL, PD, validation, and manufacturing teams to ensure world‑class testability and silicon quality.

You will lead scalable DFT methodologies, drive state‑of‑the‑art architectures for scan, compression, MBIST/LBIST, boundary scan, and in‑system test, while steering multi‑die and

Qualifications

• 15+ years of industry experience with DFT architecture leadership.
• 10+ years architecting and implementing DFT for complex SoC/FPGA/ASIC designs.
• 10+ years in scan architecture, ATPG, compression, MBIST, LBIST, and hierarchical DFT.
• 10+ years RTL-to-GDS DFT integration including scan insertion and STA constraints.
• Experience with IEEE IJTAG/JTAG standards and advanced fault models is a plus.

Responsibilities

• DFT Strategy Ownership — Define and drive long-term DFT architecture for multi-die products.
• Methodology Leadership — Develop scalable DFT flows across RTL, gate-level, and multi-die environments.
• Advanced DFT Architecture — Architect scan, compression, ATPG, MBIST/LBIST, and boundary scan solutions.
• Multi-Die & Packaging DFT — Drive planning for 2.5D/3D ICs, chiplets, and heterogeneous systems.
• Cross-Functional Integration — Collaborate with architecture, RTL, PD, validation, and manufacturing.
• DFT Governance — Establish guidelines, test specs, timing constraints, and signoff criteria.
• Silicon Debug Leadership — Lead root-cause analysis for pre- and post-silicon issues.
• Manufacturing Test Optimization — Improve coverage, test time, yield, and power-aware testing.
• Technology Innovation — Adopt new DFT technologies and automation; mentor engineers.

Skills

DFT architecture

ATPG

MBIST/LBIST

RTL-to-GDS DFT

Boundary scan

2.5D/3D DFT

Scripting (Python)

Cross-functional leadership

Education

Bachelor’s degree in Electrical Engineering or related field

Master’s degree preferred

Tools

Synthesis tools

ATPG tools

Debug/Simulation tools

Formal verification tools

Job description

## DFT ArchitectApplylocations: Penang 15, Penang, Malaysiatime type: Full timeposted on: Posted Todayjob requisition id: R02681# **Job Details:**### ## **Job Description:**The **DFT Architect** at Altera is a senior technical authority responsible for defining, driving, and governing next‐generation **DFT architecture** across Altera’s most advanced FPGA, SoC, and multi‐die silicon platforms. This role sits at the forefront of innovation in high‐performance compute, AI acceleration, advanced packaging, and heterogeneous integration.You will own the end‐to‐end **DFT strategy** for complex, large‐scale silicon programs and influence technical direction across multiple product generations. You will architect scalable, robust, and forward‐looking DFT solutions spanning scan, compression, MBIST/LBIST, hierarchical DFT, IJTAG/IEEE standards, silicon debug, and production test optimization. You will partner deeply with architecture, RTL, physical design, validation, product engineering, and manufacturing teams to ensure world‐class testability, manufacturability, and silicon quality.This role requires exceptional depth in modern DFT methodologies, strong architectural vision, and the ability to drive alignment across broad engineering organizations. You will mentor teams, shape methodology roadmaps, and represent DFT as a key decision‐maker in silicon architecture and execution.**Key Responsibilities*** **DFT Strategy Ownership** — Define and drive the long‐term DFT architecture for FPGA, SoC, processor, DSP, SERDES, IO, and multi‐die/chiplet‐based products.* **Methodology Leadership** — Lead development of scalable DFT methodologies and flows across RTL, gate‐level, hierarchical, and multi‐die integration environments.* **Advanced DFT Architecture** — Architect state‐of‐the‐art scan, compression, ATPG, MBIST, LBIST, boundary scan, and in‐system test solutions to meet aggressive coverage, quality, and cost goals.* **Multi‐Die & Advanced Packaging DFT** — Drive DFT planning and integration for 2.5D/3D ICs, chiplets, and heterogeneous multi‐die systems.* **Cross‐Functional Integration** — Collaborate with architecture, RTL, PD, STA, validation, and product engineering teams to ensure seamless DFT integration throughout the design lifecycle.* **DFT Governance** — Establish and enforce DFT guidelines, test specifications, timing constraints, and signoff criteria across large engineering programs.* **Silicon Debug Leadership** — Lead root‐cause analysis for pre‐silicon and post‐silicon test failures, yield issues, and manufacturing escapes.* **Manufacturing Test Optimization** — Optimize production test strategies for coverage, test time, yield improvement, power‐aware test, and overall efficiency.* **Technology Innovation** — Drive adoption of next‐generation DFT technologies, automation, and best practices to improve productivity and scalability.* **Technical Mentorship** — Mentor DFT engineers and provide technical leadership across multiple programs.* **EDA & Tool Strategy** — Partner with EDA vendors and internal methodology teams to evaluate, influence, and deploy advanced DFT tool capabilities.### ## **Qualifications:**Min Qualification:* Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with **15+ years** of industry experience.* **10+ years** architecting and implementing DFT solutions for complex SoC, FPGA, ASIC, or multi‐die designs.* **10+ years** experience in scan architecture, ATPG, compression, MBIST, LBIST, boundary scan, and hierarchical DFT.* **10+ years** experience with RTL‐to‐GDS DFT integration including scan insertion, STA constraints, low‐power DFT, and gate‐level verification.* **10+ years** experience with industry‐standard EDA tools for synthesis, scan insertion, ATPG, simulation/debug, formal verification, and STA.* **10+ years** experience supporting silicon bring‐up, manufacturing test flows, yield analysis, and failure debug.* **10+ years** experience developing DFT automation using scripting languages (Perl, Python, TCL).* **10+ years** experience providing technical leadership and driving cross‐functional alignment.**Preferred Qualifications*** Master’s degree in Electrical Engineering, Computer Engineering, or related field.* Experience with advanced fault models, diagnosis, and silicon analytics.* Experience with 2.5D/3D ICs, chiplet architectures, and high‐speed IO/SerDes DFT.* Familiarity with IEEE DFT standards including IJTAG (1687), JTAG (1149.x), and embedded instrumentation.* Experience with power‐aware DFT, low‐power ATPG, and large‐scale test optimization.* Experience with developing highly efficient & scalable DFT methodology & flows that incorporates AI technologies.* Experience mentoring teams and influencing DFT strategy across multiple product families.### ## **Job Type:**Regular### ## **Shift:**Shift 1 (Malaysia)### ## **Primary Location:**Penang 15, Penang, Malaysia### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.**About Altera**Altera: Accelerating InnovatorsAltera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.