Senior Package Design Engineer – Advanced IC Packaging

AMD; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

AMD in Penang, Malaysia, seeks a Senior or Staff Package Design Engineer to own advanced IC package design from concept through tape-out. You will collaborate with SoC, silicon, signal integrity, power integrity, and thermal teams to meet electrical, mechanical, and cost targets for high-speed interfaces such as LPDDR5X/LPDDR6, PCIe, and die-to-die links.

You will set design methodology, mentor engineers, and drive DFX into the packaging process while working with suppliers on flows and

Qualifications

• 5–10 years of relevant experience in IC or package design.
• Experience with high-speed interfaces (LPDDR, PCIe, SerDes, etc.).
• Familiarity with substrate design flows (Cadence APD/SIP, Allegro).
• Experience in bump/ball map planning, layer stack-up, and design rule management.

Responsibilities

• Execute package substrate design from concept through production release, including floorplanning, routing, and stack-up definition.
• Define and implement package architecture based on electrical, thermal, and mechanical requirements.
• Work with chip, board, and system teams to optimize I/O planning and interface signal integrity.
• Conduct design feasibility studies and trade-off analysis for performance, cost, and reliability.
• Drive DFX (Design for Manufacturability, Assembly, and Test) into the package design process.

Skills

Package design

Signal integrity

Power integrity

Thermal analysis

Scripting for automation

Cross-functional collaboration

Education

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

Tools

Cadence APD/SIP

Allegro

Ansys HFSS

SIwave

Q3D

Cadence Sigrity

Keysight ADS

Job description

AMD in Penang, Malaysia, seeks a Senior or Staff Package Design Engineer to own advanced IC package design from concept through tape-out. You will collaborate with SoC, silicon, signal integrity, power integrity, and thermal teams to meet electrical, mechanical, and cost targets for high-speed interfaces such as LPDDR5X/LPDDR6, PCIe, and die-to-die links.

You will set design methodology, mentor engineers, and drive DFX into the packaging process while working with suppliers on flows and