Staff Package Design Engineer — High-Speed IC Packaging

AMD; George Town; On-site; MYR 120,000 - 180,000; Full time

Benefits offered by this job

AMD Benefits

Job summary

AMD Penang is seeking a Senior or Staff Package Design Engineer to own the design of advanced IC packages from concept through tape-out and production. You will collaborate with SoC, silicon, SI, PI, thermal and manufacturing teams to meet targets for high-speed interfaces such as LPDDR5X/LPDDR6, PCIe, and die-to-die links.

The role requires 5–10 years in IC or package design, strong understanding of substrate design flows, and proficiency with tools like Cadence and Ansys.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Mechanical/Materials-related field.
• 5–10 years of IC or package design experience.
• Experience with high-speed interfaces (LPDDR, PCIe, SerDes, HBM).

Responsibilities

• Own package substrate design from concept through production release.
• Define and implement package architecture to meet electrical, thermal, and mechanical requirements.
• Collaborate with chip, board, and system teams to optimize I/O planning and interface signal integrity.
• Drive DFX (Design for Manufacturability, Assembly and Test) in the package design process.
• Perform modelling extraction for SI/PI and perform stack-up tuning.

Skills

High-speed interfaces

Substrate design flows

Bump/ball map planning

Manufacturing constraints

Problem solving

Cross-functional collaboration

Signal integrity

Power integrity

Thermal considerations

Design automation tools

Education

Electrical Engineering / Mechanical Engineering / Materials Science degree

Tools

Cadence Allegro

Ansys HFSS

SIwave

Q3D

Keysight ADS

Sigrity

Job description

AMD Penang is seeking a Senior or Staff Package Design Engineer to own the design of advanced IC packages from concept through tape-out and production. You will collaborate with SoC, silicon, SI, PI, thermal and manufacturing teams to meet targets for high-speed interfaces such as LPDDR5X/LPDDR6, PCIe, and die-to-die links.

The role requires 5–10 years in IC or package design, strong understanding of substrate design flows, and proficiency with tools like Cadence and Ansys.