Design Verification Engineer

Kosmic Technologies; Bayan Lepas; On-site; MYR 180,000 - 240,000; Full time

Job summary

Kosmic Technologies is seeking an experienced verification engineer to drive planning, development and execution of verification and validation across IP, FPGA, subsystem and full-chip levels. You will create tests, conformance plans and coverage strategies, and collaborate with cross-functional teams to validate designs on hardware.

Strong RTL/VHDL knowledge and scripting skills are essential for this senior role.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering or an equivalent discipline.
• More than five years of experience in IC design verification.
• Experience creating and executing verification and validation plans.
• Experience creating testbenches for design verification and validation according to test plans.
• Knowledge of verification tools and methodologies.
• Familiarity with RTL design using Verilog and/or VHDL.
• Familiarity with advanced verification methodologies, including UVM, OVM, VMM, SystemVerilog, constrained-random verification, assertion-based verification and functional coverage techniques.
• Knowledge of IP protocols, such as memory interface protocols including DDR and HBM, or high-speed interfaces including PCIe and Ethernet.
• Familiarity with Perl, Tcl, Python and shell scripting.
• Strong debugging, problem-solving and analytical skills.
• Experience mentoring or leading a verification or validation team is an advantage.

Responsibilities

• Create verification and validation plans based on IP and FPGA architecture specifications, covering functional, system-level and full-chip perspectives.
• Develop IP, subsystem, system-level and full-chip testbenches, tests and coverage goals based on design specifications.
• Review verification results against coverage goals, track progress and improve tests to achieve the required coverage.
• Support cross-functional teams with IP functional validation and bring-up testing on actual FPGA hardware.
• Standardise verification and validation frameworks, drive system test design implementation and lead overall IP system validation on hardware.
• Define and develop verification and validation tools and flows to reduce verification time and improve productivity.
• Interface with third-party vendors to evaluate the latest industry tools and methodologies.
• Apply advanced verification and validation techniques to achieve high quality, productivity and time-to-market performance.

Skills

RTL design (Verilog/VHDL)

UVM/SystemVerilog

Verification methodologies

Scripting: Perl/Tcl/Python

Debugging & analytical skills

Mentoring / leadership (advantage)

Education

Bachelor's or Master's in Electrical/Electronics Engineering

Tools

Verilog

VHDL

UVM

SystemVerilog

Job description

Join an engineering team responsible for planning and delivering comprehensive verification and validation activities across IP, FPGA, subsystem, system-level and full-chip designs. This role will drive robust verification strategies, improve validation frameworks and tools, and support high-quality delivery within demanding productivity and time-to-market goals.

Key responsibilities

Create verification and validation plans based on IP and FPGA architecture specifications, covering functional, system-level and full-chip perspectives.

Develop IP, subsystem, system-level and full-chip testbenches, tests and coverage goals based on design specifications.

Review verification results against coverage goals, track progress and improve tests to achieve the required coverage.

Support cross-functional teams with IP functional validation and bring-up testing on actual FPGA hardware.

Standardise verification and validation frameworks, drive system test design implementation and lead overall IP system validation on hardware.

Define and develop verification and validation tools and flows to reduce verification time and improve productivity.

Interface with third-party vendors to evaluate the latest industry tools and methodologies.

Apply advanced verification and validation techniques to achieve high quality, productivity and time-to-market performance.

What we're looking for

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering or an equivalent discipline.

More than five years of experience in IC design verification.

Experience creating and executing verification and validation plans.

Experience creating testbenches for design verification and validation according to test plans.

Knowledge of verification tools and methodologies.

Familiarity with RTL design using Verilog and/or VHDL.

Familiarity with advanced verification methodologies, including UVM, OVM, VMM, SystemVerilog, constrained-random verification, assertion-based verification and functional coverage techniques.

Knowledge of IP protocols, such as memory interface protocols including DDR and HBM, or high-speed interfaces including PCIe and Ethernet.

Familiarity with Perl, Tcl, Python and shell scripting.

Strong debugging, problem-solving and analytical skills.

Experience mentoring or leading a verification or validation team is an advantage.