Senior CAD Flow Engineer: RTL-to-GDSII Optimizer

UST Malaysia; Bayan Lepas; On-site; MYR 250,000 - 360,000; Full time

Job summary

UST Malaysia seeks a highly motivated CAD Flow Engineer to develop, maintain, and enhance Physical Design implementation flows for advanced-node ASIC/SoC projects.

The role collaborates with Physical Design, STA, DFT, RTL, and CAD teams to deliver robust methodologies that boost QoR, productivity, and turnaround time. Strong scripting and Linux experience are essential for tool integration and automation.

Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related discipline.
• 5-8 years of experience in VLSI CAD, Physical Design, Implementation Methodology, or Design Automation.
• Strong understanding of digital ASIC implementation flows from RTL to GDSII.
• Hands-on experience with Synopsys Fusion Compiler, ICC2, Formality, Design Compiler.
• Strong scripting expertise in TCL (mandatory), Python, Shell scripting.

Responsibilities

• Develop, maintain, and support Physical Design implementation flows across advanced process nodes.
• Customize and optimize flows using Synopsys Fusion Compiler, PrimeTime, ICC2, Formality, and related EDA tools.
• Design and maintain automation frameworks using TCL, Python, Perl, and Shell scripting.
• Create reusable infrastructure for synthesis, floorplanning, placement, CTS, routing, timing closure, and signoff activities.
• Develop QoR tracking, regression, reporting, and design health monitoring solutions.
• Debug flow issues, tool crashes, runtime bottlenecks, and methodology-related challenges.
• Collaborate with implementation teams to improve timing, power, area, congestion, and turnaround time.
• Enable new tool releases and drive tool qualification across projects.
• Develop methodologies for MCMM timing analysis, ECO flows, and signoff convergence.
• Work closely with EDA vendors to investigate tool issues and evaluate new features.
• Support deployment of advanced-node implementation methodologies (5nm, 3nm, and beyond).
• Create and maintain user documentation, flow guidelines, and training materials.

Skills

VLSI CAD

Physical Design

Implementation Methodology

Design Automation

TCL

Python

Shell scripting

Linux/Unix

EDA Tools

Education

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related discipline

Tools

Synopsys Fusion Compiler

PrimeTime

ICC2

Formality

Design Compiler

Job description

UST Malaysia seeks a highly motivated CAD Flow Engineer to develop, maintain, and enhance Physical Design implementation flows for advanced-node ASIC/SoC projects.

The role collaborates with Physical Design, STA, DFT, RTL, and CAD teams to deliver robust methodologies that boost QoR, productivity, and turnaround time. Strong scripting and Linux experience are essential for tool integration and automation.